Webinars 

Custom Compiler-Visually-assisted Automation for Custom Layout
Learn about Synopsys' new full-custom solution that features a visually-assisted automation flow tuned for FinFET-based designs to speed up common design tasks, reduce iterations and enable reuse.
Chris Shaw, Technical Marketing Manager, Synopsys Fred Sendig, Synopsys Fellow, Synopsys
Apr 21, 2016
 
Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate Early Stage Dynamic Analysis
In this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.
Jack Ting, CAE, Synopsys; Manoz Palaparthi, Technical Marketing Manager, Synopsys
Feb 24, 2016
 
Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate Early Stage Dynamic Analysis (Traditional Chinese)
In this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.
Martin Liu, CAD Engineer, Sunplus Technology
Feb 24, 2016
 
Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate Early Stage Dynamic Analysis (Simplified Chinese)
In this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.
Martin Liu, CAD Engineer, Sunplus Technology
Feb 24, 2016
 
Improving Analog Verification Productivity Using Synopsys Simulation and Analysis Environment (SAE)
Learn about the comprehensive GUI-based transistor-level simulation and analysis environment that is deeply integrated with CustomSim, FineSim, and HSPICE circuit simulators.
Deepa Kannan, SAE Technical Marketing Manager, Synopsys
Feb 17, 2016
 
Synopsys Mixed-Signal IP Designers Achieve Increased Productivity Using Enhanced StarRC Netlist Reduction
Learn about StarRC's recent enhancements in RC netlist reduction & how these improvements are helping Synopsys IP developers verify the performance & integrity of their industry-leading IP portfolio.
Sunderarajan S. Mohan, Architect, Analog and Mixed Signal Circuits, Synopsys; Changli Guo, R&D Manager for Extraction Products, Synopsys
Jan 27, 2016
 
Tackle the Complexities of FinFET Library Characterization with SiliconSmart
This webinar will cover the new, innovative SiliconSmart capabilities that will enable you to work smarter in solving your toughest FinFET library characterization challenges.
Ed Lechner, Director of Marketing, Design Analysis and Sign-off Tools, Synopsys
Jan 13, 2016
 
PrimeTime POCV FinFET Designs - the NVIDIA Experience (Simplified Chinese)
Synopsys will review the PrimeTime POCV technology that helps designers reduce design margins in FinFET designs, and you will learn about NVIDIA’s latest FinFET tapeout experience with PrimeTime POCV.
James Chuang, Senior Technical Marketing Manager, Synopsys
Nov 17, 2015
 
PrimeTime POCV FinFET Designs - the NVIDIA Experience (Traditional Chinese)
Synopsys will review the PrimeTime POCV technology that helps designers reduce design margins in FinFET designs, and you will learn about NVIDIA’s latest FinFET tapeout experience with PrimeTime POCV.
James Chuang, Senior Technical Marketing Manager, Synopsys
Nov 17, 2015
 
Enabling Automotive IC Design Reliability
In this webinar, we introduce the challenges facing of designers of high-reliability ICs for the automotive market, and discuss some of the proven Galaxy Design Platform IC implementation and sign-off solutions being deployed by automotive design teams worldwide.
Steve Smith, Senior Director of Marketing, Automotive Solutions
Nov 12, 2015
 
Using PrimeTime POCV to Improve Productivity and PPA in FinFET Designs - the NVIDIA Experience
Synopsys will review the PrimeTime POCV technology that helps designers reduce design margins in FinFET designs, and you will learn about NVIDIA's latest FinFET tapeout experience with PrimeTime POCV.
Amit Goel, Senior Design Engineer, NVIDIA; Khalid Rahmat, Manager R&D, Synopsys
Oct 28, 2015
 
High Performance, High Accuracy Clock Inductance Extraction with StarRC
Learn how inductance impacts high-frequency design performance, and how StarRC’s new clock net inductance extraction feature has been specifically designed to model this new parasitic effect.
Krishna Sundaresan, Corporate Applications Engineer Director, Synopsys, Inc.
Oct 15, 2015
 
Implement ARM® Cortex®-A53 Multi-core Network Computing Reference Design on Samsung 14LPP Using Lynx
This presentation will take you through implementation of a 16 processor ARM Cortex-A53 based network computing reference design targeting Samsung’s 14LPP FinFET technology using Lynx Design System.
Chad Gamble, Lynx Design System Staff CAE, Synopsys
Sep 09, 2015
 
STMicroelectronics’ Experience: Synopsys Logic BIST for Automotive and Safety-Critical Designs
ICs targeted for safety-critical applications must be able to perform in-system self-test in compliance with functional safety standards such as ISO 26262. In this webinar, Synopsys highlights synthesis-based logic BIST that addresses the self-test requirements for safety-critical designs. Our guest speaker from STMicroelectronics presents results and details of Synopsys’ test solution successfully deployed on production designs.
Cinzia Bartolommei, Senior DFT Engineer, STMicroelectronics; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Jul 30, 2015
 
STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95%
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
Sebastien Marchal, Principal Engineer, STMicroelectronics; Stephan Mahnke, Staff Corporate Applications Engineer, Synopsys
Jul 29, 2015
 
STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95% - Traditional Chinese
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
James Chuang, Senior Technical Marketing Manager, Synopsys
Jul 29, 2015
 
STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95% - Simplified Chinese
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
James Chuang, Senior Technical Marketing Manager, Synopsys
Jul 29, 2015
 
Improve Productivity And Schedule Predictability With Accurate And Timely Status Reports Using Lynx Design Systems
Learn how Lynx' Design Tracker, a new data reporting feature, enables easy access to relevant data to provide a significant boost to designer’s productivity and help effectively manage project schedules.
Chris Smith, Lynx Design System Staff CAE, Synopsys
May 13, 2015
 
Qualcomm Achieves Significantly Faster TAT with StarRC Ultra-scalable SMC Solution
Qualcomm and Synopsys will discuss the latest productivity features inside StarRC that enabled Qualcomm to achieve significant speedup in extraction and faster design closure.
Khusro Sajid, Sr. Staff Engineer, Qualcomm; Arindam Chatterjee, Manager, R&D, Synopsys;
Apr 28, 2015
 
Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO – with Samsung case study
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Synopsys
Apr 22, 2015
 
Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO - with Samsung case study (Traditional Chinese)
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Synopsys
Apr 22, 2015
 
Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO – Samsung (Simplified Chinese)
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Synopsys
Apr 22, 2015
 
HSPICE Tips & Tricks Webisode Series
Learn from Synopsys applications engineers how to get the most out of HSPICE analysis. Topics will include how to most effectively use S-element, eye diagrams, IBIS-AMI, RUNLVL, and more. New mini webinars will premiere monthly.
Ted Mido, Principal Engineer, HSPICE R&D, Synopsys
Nov 03, 2014
 
Samsung Saves 20% Total Power on FinFET Designs with PrimeTime Signoff-driven ECO - Simplified Chinese
Join Synopsys as they discuss physically-aware ECO power recovery for advanced designs. Learn how Samsung reduced total power by 20% using PrimeTime ECO’s latest power recovery technology.
James Chuang, Technical Marketing Manager, Synopsys
Oct 22, 2014
 
Samsung Saves 20% Total Power on FinFET Designs with PrimeTime Signoff-driven ECO - Traditional Chinese
Join Synopsys as they discuss physically-aware ECO power recovery for advanced designs. Learn how Samsung reduced total power by 20% using PrimeTime ECO’s latest power recovery technology.
James Chuang, Technical Marketing Manager, Synopsys
Oct 22, 2014
 
Samsung Saves 20% Total Power on FinFET Designs with PrimeTime Signoff-driven ECO
Join Synopsys as they discuss physically-aware ECO power recovery for advanced designs. Learn how Samsung reduced total power by 20% using PrimeTime ECO's latest power recovery technology.
Vivek Ghante, Senior Corporate Applications Engineer, Synopsys; James Chuang, Technical Marketing Manager, Synopsys
Oct 01, 2014
 
Increase Designer Productivity and Accelerate SoC Design Schedule Through Flow Automation
The complexities of advanced SoC design constantly challenge tape-out timelines. Synopsys' Lynx Design System can simplify and automate flows for many critical implementation and validation tasks, enabling engineers to focus on achieving performance goals. This webinar will introduce you to how customers such as Altera are leveraging Lynx in their design flows to lower risk and improve predictability. Additionally, you will learn about innovative and sophisticated automation solutions for design QoR analysis, correlation and regression that accelerate design schedules.
Lydia Lee, Lynx Design System Staff CAE, Synopsys
Sep 10, 2014
 
Imagination and Synopsys: Reduce Dynamic Power and Area up to 50% on a GHz+ MIPS Core Implementation
In this webinar, Imagination Technologies will share how their selection of standard cell architecture and use of several dynamic power techniques available in Design Compiler and IC Compiler helped them achieve optimal power and area savings for their MIPS family of CPU cores.
Maya Mohan, Hardware Design Engineer, Imagination Technologies and Jeffrey Lee, CAE Manager, Power Compiler, Synopsys
Jul 10, 2014
 
Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow - Simplified Chinese
Simplified Chinese: Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Chung Yang, CAE, Synopsys
May 28, 2014
 
Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow - Traditional Chinese
Traditional Chinese: Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Chung Yang, CAE, Synopsys
May 28, 2014
 
Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow
Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Carol Scemanenco, Senior Staff Engineer, Synopsys
May 27, 2014
 
Latest Advances in PrimeRail In-Design Vector Free Rail Analysis
See the latest innovations in PrimeRail's In-Design solution including rail integrity and static/dynamic analysis that enable designers to achieve significant productivity in advanced node designs.
Jason Binney, Principle CAE, Synopsys
May 14, 2014
 
Counting Down to 10 nm: GLOBALFOUNDRIES and Synopsys Perspective on Future Extraction
GLOBALFOUNDRIES and Synopsys will discuss the implications for extraction as foundries move to the next level of die shrink at 10nm.
Jongwook Kye, Fellow, GLOBALFOUNDRIES; Beifang Qiu, Senior R&D Manager, Synopsys
Apr 30, 2014
 
Accelerating Time to a Quality Floorplan: Cisco Systems and Synopsys Share Their Insights
Learn how IC Compiler’s new Data Flow Analysis (DFA) technology enables designers to accelerate time to a quality floorplan. Cisco Systems shares their experiences deploying this technology on a 100+ million gate ASIC to reduce floorplanning iterations with ASIC vendors and quickly identify and validate macro placement for the best quality of results.
Krishna Kumar Gundavarapu, Technical Leader, Cisco; Steve Kister, Technical Marketing Manager, Synopsys
Apr 23, 2014
 
Easy and Intuitive Analysis of Design Metrics with the Lynx Design System's QoR Viewer
Immediate access to pertinent design metrics enables better design decisions and faster time to results. Learn how Lynx enables you to customize metric review to highlight key data material to achieving design goals.
Aditya Ramachandran, Lynx Design System Staff CAE, Synopsys
Feb 19, 2014
 


NewsArticlesBlogsSuccess StoriesWhite PapersWebinarsVideos