Webinars 

STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95%
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
Sebastien Marchal, Principal Engineer, STMicroelectronics; Stephan Mahnke, Staff Corporate Applications Engineer, Synopsys
Jul 29, 2015
 
STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95% - Traditional Chinese
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
James Chuang, Senior Technical Marketing Manager, Synopsys
Jul 29, 2015
 
STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95% - Simplified Chinese
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
James Chuang, Senior Technical Marketing Manager, Synopsys
Jul 29, 2015
 
Improve Productivity And Schedule Predictability With Accurate And Timely Status Reports Using Lynx Design Systems
Learn how Lynx' Design Tracker, a new data reporting feature, enables easy access to relevant data to provide a significant boost to designer’s productivity and help effectively manage project schedules.
Chris Smith, Lynx Design System Staff CAE, Synopsys
May 13, 2015
 
Qualcomm Achieves Significantly Faster TAT with StarRC Ultra-scalable SMC Solution
Qualcomm and Synopsys will discuss the latest productivity features inside StarRC that enabled Qualcomm to achieve significant speedup in extraction and faster design closure.
Khusro Sajid, Sr. Staff Engineer, Qualcomm; Arindam Chatterjee, Manager, R&D, Synopsys;
Apr 28, 2015
 
Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO – with Samsung case study
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Synopsys
Apr 22, 2015
 
Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO - with Samsung case study (Traditional Chinese)
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Synopsys
Apr 22, 2015
 
Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO – Samsung (Simplified Chinese)
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Synopsys
Apr 22, 2015
 
HSPICE Tips & Tricks Webisode Series
Learn from Synopsys applications engineers how to get the most out of HSPICE analysis. Topics will include how to most effectively use S-element, eye diagrams, IBIS-AMI, RUNLVL, and more. New mini webinars will premiere monthly.
Ted Mido, Principal Engineer, HSPICE R&D, Synopsys
Nov 03, 2014
 
Samsung Saves 20% Total Power on FinFET Designs with PrimeTime Signoff-driven ECO - Simplified Chinese
Join Synopsys as they discuss physically-aware ECO power recovery for advanced designs. Learn how Samsung reduced total power by 20% using PrimeTime ECO’s latest power recovery technology.
James Chuang, Technical Marketing Manager, Synopsys
Oct 22, 2014
 
Samsung Saves 20% Total Power on FinFET Designs with PrimeTime Signoff-driven ECO - Traditional Chinese
Join Synopsys as they discuss physically-aware ECO power recovery for advanced designs. Learn how Samsung reduced total power by 20% using PrimeTime ECO’s latest power recovery technology.
James Chuang, Technical Marketing Manager, Synopsys
Oct 22, 2014
 
Samsung Saves 20% Total Power on FinFET Designs with PrimeTime Signoff-driven ECO
Join Synopsys as they discuss physically-aware ECO power recovery for advanced designs. Learn how Samsung reduced total power by 20% using PrimeTime ECO's latest power recovery technology.
Vivek Ghante, Senior Corporate Applications Engineer, Synopsys; James Chuang, Technical Marketing Manager, Synopsys
Oct 01, 2014
 
Increase Designer Productivity and Accelerate SoC Design Schedule Through Flow Automation
The complexities of advanced SoC design constantly challenge tape-out timelines. Synopsys' Lynx Design System can simplify and automate flows for many critical implementation and validation tasks, enabling engineers to focus on achieving performance goals. This webinar will introduce you to how customers such as Altera are leveraging Lynx in their design flows to lower risk and improve predictability. Additionally, you will learn about innovative and sophisticated automation solutions for design QoR analysis, correlation and regression that accelerate design schedules.
Lydia Lee, Lynx Design System Staff CAE, Synopsys
Sep 10, 2014
 
Advanced Mixed-Signal Design and Verification of Smartcar ICs
In this webinar, Micronas and Synopsys discuss the breadth of automotive IC applications, challenges in design implementation and verification and the solutions that stemmed from their collaboration.
Mario Anton, Micronas; Gernot Koch, Micronas; Marco Casale-Rossi, Synopsys
Jul 31, 2014
 
Imagination and Synopsys: Reduce Dynamic Power and Area up to 50% on a GHz+ MIPS Core Implementation
In this webinar, Imagination Technologies will share how their selection of standard cell architecture and use of several dynamic power techniques available in Design Compiler and IC Compiler helped them achieve optimal power and area savings for their MIPS family of CPU cores.
Maya Mohan, Hardware Design Engineer, Imagination Technologies and Jeffrey Lee, CAE Manager, Power Compiler, Synopsys
Jul 10, 2014
 
Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow - Simplified Chinese
Simplified Chinese: Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Chung Yang, CAE, Synopsys
May 28, 2014
 
Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow - Traditional Chinese
Traditional Chinese: Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Chung Yang, CAE, Synopsys
May 28, 2014
 
Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow
Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Carol Scemanenco, Senior Staff Engineer, Synopsys
May 27, 2014
 
Latest Advances in PrimeRail In-Design Vector Free Rail Analysis
See the latest innovations in PrimeRail's In-Design solution including rail integrity and static/dynamic analysis that enable designers to achieve significant productivity in advanced node designs.
Jason Binney, Principle CAE, Synopsys
May 14, 2014
 
FineSim Technology for Analog and Full-Chip Simulation - A Micron Case Study
Learn about FineSim’s transient analysis advantage and the rich feature set that that combines SPICE and FastSPICE simulation technology in one single environment used for memory design at Micron.
Raed Sabbah, Sr. Design Engineer, Embedded Solutions Group, Micron Technology
May 08, 2014
 
Counting Down to 10 nm: GLOBALFOUNDRIES and Synopsys Perspective on Future Extraction
GLOBALFOUNDRIES and Synopsys will discuss the implications for extraction as foundries move to the next level of die shrink at 10nm.
Jongwook Kye, Fellow, GLOBALFOUNDRIES; Beifang Qiu, Senior R&D Manager, Synopsys
Apr 30, 2014
 
Accelerating Time to a Quality Floorplan: Cisco Systems and Synopsys Share Their Insights
Learn how IC Compiler’s new Data Flow Analysis (DFA) technology enables designers to accelerate time to a quality floorplan. Cisco Systems shares their experiences deploying this technology on a 100+ million gate ASIC to reduce floorplanning iterations with ASIC vendors and quickly identify and validate macro placement for the best quality of results.
Krishna Kumar Gundavarapu, Technical Leader, Cisco; Steve Kister, Technical Marketing Manager, Synopsys
Apr 23, 2014
 
Easy and Intuitive Analysis of Design Metrics with the Lynx Design System's QoR Viewer
Immediate access to pertinent design metrics enables better design decisions and faster time to results. Learn how Lynx enables you to customize metric review to highlight key data material to achieving design goals.
Aditya Ramachandran, Lynx Design System Staff CAE, Synopsys
Feb 19, 2014
 


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