QuickCap NX 

3D Field Solver 
QuickCap NX is the gold standard 3D Field Solver solution for advanced 14nm FinFET and beyond process technologies.
  • Field solver solution for early process technology node exploration and parasitic modeling development
  • Advanced random-walk algorithm offers self-capacitance, coupling capacitance and distributed capacitance extraction for test structures and critical nets
  • Supports detailed process modeling of complex geometries and process effects for accurate analysis of device and interconnect parasitics at 14nm and below
  • Used by Foundries for high-accuracy 3D FinFET modeling using uniquely detailed silicon profiles
  • 3D graphical viewer allows visibility into the exact process profile being modeled
  • Faster runtime enabled by multicore processing, tiling, bounded nets and hierarchical extraction for increased designer productivity

QuickCap NX Datasheet

QuickCap NX is a high-accuracy 3D parasitic field solver for foundry process technology development and circuit analysis. QuickCap NX includes key capabilities that address critical design challenges that occur in 14-nm process technologies and below. QuickCap NX is also used by foundries for modeling complex FinFET middle-of-line (MEOL) parasitic effects at 14-nm and below. With its advanced process modeling features, a parallel execution mode and reference-level SPICE netlist generation and reduction capabilities, users can shorten the development cycle by more accurately predicting silicon performance.

Figure 1
Figure 1: QuickCap NX 3D field solver solution enables early process
exploration and characterization

As geometries shrink and clock frequencies increase, designers need more accurate parasitic values to reduce risk of design failure. The growing need for more accuracy makes it necessary to account for precise fringing electrostatic fields and process effects in test structures and analyzing critical cells, blocks and nets. QuickCap NX provides robust, consistent and accurate 3D capacitance extraction with capacity to handle moderately sized blocks or long critical nets. QuickCap NX's proven modeling capabilities allow users to perform accurate noise and timing analysis for robust design development and improved silicon success.

Advanced 3D Modeling and Process Development
QuickCap NX includes the ability to create 3-D physical models which precisely match actual process technology profiles. The unique capability allows foundries and early technology adopters to engage earlier to explore device parasitic capacitance effects in new technology nodes and accelerate the development schedules. An exclusive technology file encryption feature provides foundries with a secure method of sharing critical process information with their customers, allowing them to enhance the accuracy of their analysis and speedup the migration to new nodes. In addition, multicore capabilities and hierarchical processing significantly improve runtime, and a powerful 3D graphics viewer simplifies the development and debug of new complex circuit structures and technology files. As a result, QuickCap NX is broadly used in process studies, characterization and correlation across several generations of process nodes, and to support highly accurate device-level SPICE simulations.

FinFET modeling at 14-nm
Several changes are introduced by FinFET transistor architecture at 14nm and below. FinFETs are able to achieve better control over the source-drain channel because the gate encloses the channel on three sides, resulting in higher mobility, greater drive strength, lower switching currents, and lower leakage currents. This 3D architecture also introduces more complex geometries and many new capacitive elements that require highly accurate modeling. QuickCap NX's geometry pre-processing engine provides a highly accurate physical profile of the FinFET for modeling, and its graphical viewer allows users to see exactly how the device will be modeled. Finally, the core 3-D field-solver engine of QuickCap NX accurately extracts the capacitance values from the model. Combined, these capabilities allow QuickCap NX to provide the necessary precision to model FinFET devices at 16-nm and below, and as a result it has been adopted by leading foundries for this purpose.

Figure 2
Figure 2: QuickCap NX is used by foundries for advanced 14-nm FinFET modeling

Powerful Geometry Processing Engine
The geometry pre-processor capability "gds2cap" translates the 2D layout data into a 3D representation and reduced SPICE netlist with resistance and capacitance. The gds2cap capability includes a flexible polygon-processing engine that handles multiple conformal dielectrics, non-Manhattan geometries, non-planar metals, metal fill, process effects (OPC, CMP, Trapezoidal wire), device recognition, resistance extraction and exclusion of device capacitances. QuickCap NX takes the 3D representation and the netlist output from the gds2cap interface, produces an output file containing self and couplingcapacitance values and replaces the capacitance values in the netlist with accurately computed values from QuickCap NX.

Figure 3
Figure 3: QuickCap NX provides precise physical models of process effects

Proven Parasitic Capacitance Extraction
QuickCap NX has demonstrated close correlation to silicon measurements at various process nodes. Its advanced modeling, including modeling of optical and copper effects as well as indie process variations, enable increased accuracy. The validation of QuickCap NX's silicon accuracy by foundries has lead to its wide use in early process technology development and device characterization.

For advanced users, QuickCap NX also provides a dial-in accuracy and errorbounds reporting on each net, providing the flexibility and control for their target application needs.

Handling Large Layouts
QuickCap NX provides multiple techniques to enable critical net analysis in designs too large to fit in memory. Runtime or memory use can be reduced by using tiling, bounded nets, hierarchical processing, multicore processing or a combination of these techniques.

Key Features Summary
  • 3D modeling of FinFET devices at 14-nm and below
  • Accurate extraction of self-coupling and distributed capacitance
  • Robust and accurate handling of complex geometries including non- Manhattan structures, conformal dielectrics and floating metal
  • Advanced process effects for in-die process variation, optical and copper effects
  • 3D graphics viewer
  • Dial-in accuracy and error bounds reporting for each net
  • Low memory usage independent of accuracy
  • Runtime independent of net length
  • Exclusion of device capacitance and optional inclusion of device fringe capacitance
  • Parasitic reduction
  • Flat and hierarchical processing
  • Tile or bounded net analysis
  • Multicore processing
  • Technology file encryption
  • GDSII or scripted text
  • Output
  • Back annotated SPICE netlist
  • Capacitance summary in a matrix
  • 3D graphics viewer
  • Platform/OS
  • 64 bit Solaris and Linux

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