Synopsys at ITC 2012 

Accelerate Time-to-Quality 
Synopsys 20th Annual Test SIG
Monday, November 5, 2012
6:30 p.m. – 9:30 p.m.
Disney's Grand Californian Hotel, Anaheim, CA
Sequoia Ballroom

Synopsys customers are cordially invited to attend Synopsys' 20th Annual Test SIG event at ITC 2012. Appetizers and cocktails will be served, followed by a sit-down dinner.

Phil Nigh, Senior Technical Staff at IBM will host the event and test experts from leading companies will present on how they are deploying Synopsys' synthesis-based test solution to address their most challenging test needs. Speakers include:

  • Kun Young Chung, Samsung Electronics
  • Rao Desineni, GLOBALFOUNDRIES
  • Rory Fisher, Avago Technologies

After the presentations, you will have the opportunity to mingle with Synopsys R&D staff to discuss any of your test-related questions.

Prize Drawing: As an attendee, you will be entered in a raffle to win a Google Nexus 7 Tablet.

Seating is limited, so please register early for this important event.

Register Now!

The Grand Californian is a 5-minute walk from Disneyland Hotel.
Map: Disneyland Hotel to Grand Californian Hotel


ITC 2012

Test Week: Sunday, November 4 – Friday, November 9
Conference and exhibition: Tuesday, November 6 – Thursday, November 8
Exhibit Hours:
Tuesday, November 6, 10:30 a.m. – 5:30 p.m.
Wednesday, November 7, 9:30 a.m. – 4:30 p.m.
Thursday, November 8, 9:30 a.m. – 1:00 p.m.

Synopsys Booth # 111
Come and see why Synopsys’ synthesis-based test solution provides the fastest and most cost-effective path to high-quality manufacturing tests and high-volume silicon. It’s comprised of DFTMAX™ compression and TetraMAX® ATPG for power-aware logic test and physical diagnostics, DesignWare® STAR Memory System® for test, repair and diagnostics of embedded memories, DesignWare IP with built-in self-test of high-speed SERDES interfaces, Yield Explorer for design-centric yield analysis, and Camelot™ for CAD navigation. We’ll demonstrate how you can:


  • Lower the cost of testing multi-core ARM® processor-based designs while still meeting your aggressive design goals
  • Efficiently test thousands of memories on-chip and target memory defects at 20nm and below
  • Accelerate yield ramp with design-centric volume diagnostics and collaborative yield analysis
  • Speed physical failure analysis with the de facto standard in CAD navigation

iPad

Prize drawing Tuesday and Wednesday in the Synopsys booth!
Win an Apple iPad. Stop by the Synopsys booth (#111) to enter the raffle.

Synopsys Activities at ITC 2012

Tuesday, November 6, 4:00 p.m. – 5:30 p.m.
Ph.D. Thesis Competition Forum: Final Round
Chair: Yervant Zorian, Synopsys

Wednesday, November 7, 8:30 a.m.– 10:00 a.m.
Session 9: Scan Compression
Chair: Adam Cron, Synopsys

9.2 "Hybrid Selector for High-X Scan Compression"
Presenters: Peter Wohl, John Waicukauski, Frederic Neuveux, Synopsys; Jon Colburn, NVIDIA

Thursday, November 8, 2:00 p.m. - 3:30 p.m
Panel 5: "Testing High-Frequency and Low Power Designs: Do the Standard Rules and Tools Apply"
Panelist: Adam Cron, Synopsys

Thursday, November 8, 4:00 p.m. – 6:30 p.m. & Friday, November 9, 8:00 a.m. - 4:00 p.m.
3D-Test: 3nd IEEE International Workshop on Testing Three-Dimensional Stacked ICs
General Chair: Yervant Zorian, Synopsys
Table-Top Demo: "Synopsys Test Solution for 2.5D and 3D ICs"

Thursday, November 8, 6:30 p.m. - 7:00 p.m. & Friday, November 9, 10:30 a.m. - 10:45 a.m. and 1:00 p.m. - 1:20 p.m.
3D-Test: 3nd IEEE International Workshop on Testing Three-Dimensional Stacked ICs
Poster 2: "Standardization Working Group on 3D-Test / Project P1838"
Presenters: Adam Cron, Synopsys; Erik Jan Marinissen, IMEC, BE

Friday, November 9, 9:15 a.m. – 10:30 p.m.
3D-Test: 3nd IEEE International Workshop on Testing Three-Dimensional Stacked ICs
Session 5: 3D Electronic Design Automation
10:05 a.m.: "An Effective Infrastructure IP for Memory Dies in 3D-ICs"
Presenters: Yervant Zorian, Gurgen Harutunyan, Synopsys

Friday, November 9, 10:30 a.m.
8th IEEE International Workshop on Silicon Debug and Diagnosis
Session 3, Talk 1: “Volume Diagnostics with Static Timing Analysis to Improve Yield on Transition Fault Test Patterns”
Presenters: Christophe Suzor and Salvatore Talluto, Synopsys; Nelly Feldman, ST Microelectronics

For more information about Synopsys' synthesis-based test solution, visit the Test Automation page on Synopsys.com at www.atpg.com.



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