White Papers 

More Effective Test: Slack-Based Transition Delay
Although standard transition delay testing improves defect coverage beyond levels stuck-at patterns alone can achieve, the methodology is limited in its ability to reach the test quality levels required for the latest generation of designs. In response, an improved delay test methodology, slack-based transition delay (SBTD), is being deployed by Synopsys customers as a means to achieve even higher defect coverage than standard transition delay. This white paper describes the basic principles related to SBTD, which is available in Synopsys’ synthesis-based test solution, DFTMAX and TetraMAX ATPG.
Chris Allsup, Marketing Manager, Synopsys

Low DPPM Testing for Advanced Process Nodes and FinFETs
Most design teams rely on both stuck-at and transition delay tests from automatic test pattern generation (ATPG) to meet their manufacturing test quality goals at established process nodes. At advanced nodes, process variations give rise to physical defects that require additional tests for achieving low defective parts per million (DPPM). This paper highlights low DPPM test strategies and discusses how different physical defects associated with small-geometry processes impact the delay and leakage behavior of FinFET logic gates. We then show how leading-edge capabilities in Synopsys’ TetraMAX® ATPG, such as slack-based transition delay testing and cell-aware testing, can be used to enable low DPPM testing for advanced process nodes and FinFETs.
Chris Allsup, Marketing Manager, Synopsys

Introducing DFTMAX Ultra: New Technology to Address Key Test Challenges
For most design-for-test (DFT) and test engineers, achieving very high defect coverage with minimal design impact and low manufacturing test cost are fundamental objectives. Almost all of today's large digital designs require scan compression to meet these goals. This paper explains how DFTMAX Ultra delivers new scan compression technology that further reduces test cost and simplifies design impact, providing improvements in test quality.
Rohit Kapur, Synopsys Scientist and Cy Hay, Marketing Manager, Synopsys

DFTMAX Compression Shared I/O
This joint white paper with ARM’s lead DFT architect highlights why shared I/O capability in DFTMAX compression and TetraMAX ATPG has become the preferred approach for testing multicore ARM® processor designs. The paper describes two architectural variants of shared I/O and optimizations for identical cores, presenting improvements in ATPG pattern count and runtime for quad-core ARM Cortex®-A7 and A15 processors compared with a typical, non-shared I/O approach.
Chris Allsup, Marketing Manager, Synopsys; Padmashree Takkars, Corporate Applications Engineer, Synopsys; and Teresa McLaurin, DFT Architect, ARM

Test Automation of 3D Integrated Systems
This whitepaper discusses some of the key challenges related to testing 3D integrated systems, and how early adopters can use Synopsys' synthesis-based test solution to maximize their productivity when implementing test for 3D systems.
Chris Allsup, Marketing Manager, Synopsys

Synthesis-Based Test For Maximum RTL Designer Productivity
Synopsys provides test technology embedded in synthesis, or “synthesis-based test”, to implement the key aspects of DFT for scan testing, boundary scan, embedded memory test, on-chip testing of high-speed blocks like USB and PCI Express® cores and connections to yield analysis.
Robert Ruiz, Product Marketing Manager, Synopsys

Testing Low Power Designs with Power Aware Test
The most important trend over the past decade for semiconductor design is the dominant requirement to reduce power consumption and power dissipation. Not only do competitive products require more functionality and higher performance, they must fit into increasingly smaller and more portable products.
Cy Hay, Product Manager, Synopsys

Using TetraMAX® Physical Diagnostics for Advanced Yield Analysis
Scan-based DFT is now the standard digital logic testing used on almost all SoC designs.
Cy Hay, Product Manager

Multicore and Distributed Processing With TetraMAX® ATPG
Running automatic test pattern generation (ATPG) on a single processor may take a week or longer to complete, especially for very large designs and when testing at-speed fault models. Designers and test engineers need a straightforward way to reduce ATPG runtime by many factors and deliver working test patterns in days, not weeks.
Cy Hay, Product Manager

DFTMAX Compression Backgrounder
Scan design, the ubiquitous design-for-test technology, is based on a relatively simple concept: One or more scan chains are constructed on a chip by serially tying together a set of internal registers and flip-flops.
Rohit Kapur & Robert Ruiz, Synopsys



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