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TSMC and Synopsys Present: DFTMAX Compression, Hierarchical Test and iJTAG
As the complexity of systems-on-chip increases, so does the need to leverage standards-based methodologies to implement test in a hierarchical manner, across multiple cores.
Dr. Saman Adham, Senior Manager, TSMC; Robert Ruiz, Product Marketing Manager, Synopsys; Adam Cron, Principal Engineer, Synopsys
May 23, 2013 | | | Enabling 3D-IC Integration
Hear how Xilinx is using SSI technology to deliver higher levels of integration and flexibility in FPGA products, and learn how Synopsys' silicon-proven tools are enabling 3D-IC integration.
Steve Smith, Senior Director, 3D-IC Strategy and Marketing, Synopsys; Shankar Lakka, Director of IC Design, Full-Chip FPGA Integration Group, Xilinx
Jul 18, 2012 | | | Improved Test for Pin-Limited and Multi-Voltage Designs Using DFTMAX™ Compression and TetraMAX® ATPG
Learn how to use Synopsys' synthesis-based test solution to reduce test cost and improve test quality for designs with few available test pins, and for designs with multiple power domains.
Robert Ruiz, Senior Product Marketing Manager, Synopsys; Carl Holzwarth Corporate Applications Engineering Director, Synopsys; and Brad MacMonagle Senior Staff Applications Consultant, Synopsys
May 23, 2012 | | |
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