|STMicroelectronics’ Experience: Synopsys Logic BIST for Automotive and Safety-Critical Designs|
ICs targeted for safety-critical applications must be able to perform in-system self-test in compliance with functional safety standards such as ISO 26262. In this webinar, Synopsys highlights synthesis-based logic BIST that addresses the self-test requirements for safety-critical designs. Our guest speaker from STMicroelectronics presents results and details of Synopsys’ test solution successfully deployed on production designs.
Cinzia Bartolommei, Senior DFT Engineer, STMicroelectronics; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Jul 30, 2015
|Advantest and Synopsys: Taking Test Cost Reduction to the Next Level|
In this webinar, we highlight two methodologies, multisite test and concurrent test, that minimize test application time and maximize throughput.
Dave Armstrong, Director of Business Development, Advantest; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Apr 30, 2015
|Achieving Ultra-Low DPPM: Avago Case Study|
Hear experts from Avago and Synopsys describe key advanced fault models available in Synopsys' synthesis-based test solution, DFTMAX and TetraMAX ATPG, to achieve ultra-low DPPM.
Stefano Zanatta, DFT Engineer, Avago Technologies; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Jun 26, 2014
|Dialog Semiconductor and Synopsys Present: New DFTMAX Ultra for Squeezing Out More Test Compression with Fewer Pins|
The demand for pin-limited compression is being driven by tighter form factors, the design of multicore SoCs that require few pins per core for test access, and the adoption of multisite testing as a technique to reduce test application time and cost. In this webinar, we will highlight how Synopsys’ new DFTMAX Ultra is designed from the ground up to achieve high compression using fewer digital scan pins and a minimum of one pair of scan pins. Our guest speaker will then discuss how DFTMAX Ultra is being successfully deployed to lower the cost of testing mixed-signal designs at Dialog Semiconductor.
Richard Illman, Technical Staff Member, Dialog Semiconductor; Carl Holzwarth Corporate Applications Engineering Director, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Apr 17, 2014
|TSMC & Synopsys Present: DFTMAX Compression, IEEE 1500-based Hierarchical Test & iJTAG|
As the complexity of systems-on-chip increases, so does the need to leverage standards-based methodologies to implement test in a hierarchical manner, across multiple cores.
Dr. Saman Adham, Senior Manager, TSMC; Robert Ruiz, Product Marketing Manager, Synopsys; Adam Cron, Principal Engineer, Synopsys
May 23, 2013