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DFTMAX
DFT MAX compression is a comprehensive scan compression solution that addresses the cost challenges of testing designs fabricated in 130-nm and smaller process technologies.
DFT Compiler
DFT Compiler - Synopsys' design-for-test (DFT) synthesis solution - delivers DFT transparently within Synopsys' logical and physical synthesis flows with fastest time to results.
TetraMAX ATPG
TetraMAX® ATPG automatically generates high quality manufacturing test patterns.
TEST VIDEO UPDATE
Intro to New 2013.03 Test Automation Features
ARTICLE
DFT strategy for ARM processor-based designs
Success Story
TetraMAX ATPG Boosts Test Quality at STMicroelectronics
EE TIMES ARTICLE
The Fast Track to 3D-IC Testing
White Paper
Synthesis-Based Test For Maximum RTL Designer Productivity
News
Synopsys Enhances Volume Diagnostics Solution to Accelerate Yield Ramp
Synopsys' DesignWare STAR Memory System Shipped in 1 Billion Chips
Synthesis-Based Test Technology Increases Designer Productivity
Power-Aware Test Speeds Time to Volume Production at Realtek
Synopsys DFTMAX Compression Cuts Pin-Limited Test Cost by 95 Percent at Silicon Image
Synopsys TetraMAX ATPG Cuts Test Development Schedule at Arrow Electronics
Synopsys Extends DFTMAX Compression to Reduce the Cost of Pin-Limited Test
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All Synopsys News
Articles
DFT strategy for ARM processor-based designs
20nm test demands new design-for-test and diagnostic strategies
The Fast Track to 3D-IC Testing
The Hidden Costs of Test
DFT: Essential For Power-Aware Test
Expanding Synthesis-based Test for Higher QoR and Lower Cost
Synopsys debuts DesignWare STAR ECC IP
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Datasheets
DFTMAX
DFT Compiler
TetraMAX ATPG
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White Papers
Test Automation of 3D Integrated Systems
Synthesis-Based Test For Maximum RTL Designer Productivity
Testing Low Power Designs with Power Aware Test
Using TetraMAX® Physical Diagnostics for Advanced Yield Analysis
Multicore and Distributed Processing With TetraMAX® ATPG
DFTMAX Compression Backgrounder
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Webinars
DFTMAX Compression, Hierarchical Test and iJTAG
Enabling 3D-IC Integration
Improved Test for Pin-limited and Multi-voltage Designs
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Videos
Intro to New 2013.03 Test Automation Features
Introduction to Synthesis-Based Test
Accelerate Product Ramp with TetraMAX ATPG and Yield Explorer
Pin-Limited Test
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Lynx Design System
Galaxy Platform
SNUG
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