|DFT strategy for ARM processor-based designs|
This article provides an example of an optimized DFT architecture, referred to as “shared I/O.” It is enabled by Synopsys’ synthesis-based test solution, which has been used successfully in Samsung’s multicore processor designs. The experience demonstrates that shared I/O is a better approach than the standard DFT architecture for testing multicore designs since it reduces test costs by utilizing fewer pins while providing the same or better test time reduction.
Jan 22, 2013
|20nm test demands new design-for-test and diagnostic strategies|
20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies.
Nov 05, 2012
|The Fast Track to 3D-IC Testing|
Three-dimensional integrated circuit (3D-IC) systems offer the potential to deliver significant improvements in performance, power, functional density, and form factor over other packaging integration techniques. Despite substantial progress toward realizing 3D-IC systems, a variety of design, manufacturing, packaging, and testing issues still need to be addressed before cost-effective, high-volume production can be achieved.
Jan 16, 2012
|The Hidden Costs of Test|
As complexity grows in SoCs, so does the ability to accurately test them. That helps explain why there are so many different types of tests and so much confusion about what to use to perform those tests, when to test, and where in the flows to include those tests. But what's less well known is that tests done improperly also can give false results, labeling good chips as bad - or in some cases actually killing a good chip.
Oct 06, 2011
|DFT: Essential For Power-Aware Test|
Power-aware test is a major manufacturing consideration due to the problems of increased power dissipation in various test modes, as well as test implications that come up with the usage of various low-power design technologies
Sep 08, 2011
|Expanding Synthesis-based Test for Higher QoR and Lower Cost |
Robert Ruiz, Synopsys, explains how advanced test technology is enabling designers to achieve optimal quality of results (QoR) and eliminate time-consuming iterations between design and test, to keep pace with customers' evolving requirements.
Mar 28, 2011
|Synopsys debuts DesignWare STAR ECC IP|
Synopsys chose the International Test Conference to announce an expansion of its synthesis-based test technology and announced the availability of its DesignWare STAR ECC (self test and repair error-correcting codes) IP.
Nov 06, 2010
|Synopsys to Expand Synthesis-Based Test Technology|
Synopsys announced plans to expand test technology embedded in Synopsys' RTL synthesis to address the need for higher defect coverage, lower test cost and faster yield analysis while simultaneously minimizing the impact on design goals and project schedules.
Nov 04, 2010
|Are design and test conflicting or symbiotic?”|
Although design and test goals may be fundamentally different, are they in direct conflict or are they in fact symbiotic? Read to find out the answer to this question and learn why achieving better design-for-test now requires an approach based in synthesis to enable faster and more predictable results for both design and test.
Oct 08, 2010
|Using compression to meet pin-limited test requirements|
This article looks at the industry’s growing need to maintain high scan compression with fewer test pins, and how Wolfson Microelectronics used DFTMAX compression to meet its pin-limited test requirements.
Jan 21, 2010
|Small Delay Defect Testing|
Advances in Synopsys’ TetraMAX ATPG technology have made it possible for semiconductor companies to efficiently target extremely subtle nanometer defects during manufacturing test.
This article describes the basic principles behind small delay defect (SDD) ATPG and presents failure statistics on hundreds of thousands of ICs manufactured at STMicroelectronics showing that TetraMAX’s SDD patterns achieve higher defect coverage than standard transition delay patterns.
Jun 01, 2009
|Playing it cool|
Power-aware ATPG technology controls thermal and power-rail-droop problems that can damage devices or lead to false failures during production test.
Oct 01, 2008
|Optimizing Compression in Scan-based ATPG DFT Implementations |
Implementing scan compression on-chip provides significant test cost savings, but how much compression is enough? This article introduces a comprehensive economic model unifying test data reduction and test time reduction principles that describes how to determine the optimal compression level for your designs.
Mar 01, 2007