SNUG Silicon Valley: Design Compiler Lunch and Learn 

Overcoming the Challenges of Shrinking Design Schedules vs. Increasing Complexity 

Industry experts from Samsung, Qualcomm, Cisco and Synopsys discuss how they are utilizing DC Explorer and Design Compiler Graphical to tackle the challenges of ever-increasing design complexities amidst shrinking schedules. The panelists present on how DC Explorer helps generate high-quality design data quicker by providing early visibility into design problems and results while producing a netlist to give a head start to tasks such as physical feasibility. You will hear about some of the recent advancements in DC Explorer that enable floorplan creation and design connectivity analysis at a very early design stage. Additionally, the speakers share how Design Compiler Graphical is helping them attain their design goals by delivering superior quality of results and tighter correlation to layout.

Eyal Odiz
Eyal Odiz
VP of Engineering, Synopsys
Cheal Rim
Cheal Rim
Sr. Engineer, Samsung
 
Troung Hoang
Troung Hoang
Principal Engineer/Manager, Qualcomm
Venkataraman Srinivasagam
Venkataraman Srinivasagam,
Technical Leader, Cisco
 


NewsArticlesDatasheetsSuccess StoriesWhite PapersWebinarsVideos