Design Compiler Lunch and Learn 

Overcoming the Challenges of Shrinking Design Schedules vs. Increasing Complexity 

Join us for this special lunch event at SNUG Silicon Valley to hear your peers discuss how they are utilizing DC Explorer and Design Compiler Graphical to tackle the challenges of ever-increasing design complexities amidst shrinking schedules. The panelists will discuss how DC Explorer helps generate high-quality design data quicker by providing early visibility into design problems and results while producing a netlist to give a head start to tasks such as physical feasibility. You will hear about some of the recent advancements in DC Explorer that enable floorplan creation and design connectivity analysis at a very early design stage. Additionally, the panelists will share how Design Compiler Graphical is helping them attain their design goals by delivering superior quality of results and tighter correlation to layout. Join us to see how these technologies are enabling your fellow Design Compiler users to achieve a faster, convergent early-RTL exploration to GDSII flow.

Add the Design Compiler Lunch and Learn to your SNUG Silicon Valley agenda to Register Now!
Seating is limited for this popular event, so arrive early to ensure your spot!

Cheal Rim, Sr. Engineer, Samsung
Truong Hoang, Principal Engineer/Manager, Qualcomm
Venkataraman Srinivasagam, Technical Leader, Cisco

Target audience:
RTL design, CAD and physical design engineers/managers

Prize Drawing:

Design Compiler Lunch and LearnDesign Compiler Lunch and LearnFollowing the technical presentations, raffle drawings will be held for an Apple iPad Mini and a Samsung Galaxy Tab 2.

March 26, 2013
12:00 p.m. to 1:30 p.m.

SNUG Silicon Valley
Santa Clara Conventions Center
Mission City Ballroom
5001 Great America Parkway
Santa Clara, CA 95054

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