Ensuring that complex SoCs meet manufacturing test requirements is a significant challenge. The Synopsys synthesis-based test solution maximizes productivity, providing designers, DFT engineers and product engineers with the fastest and most cost-effective path to high-quality manufacturing tests and high-volume silicon. Synthesis-based technology minimizes the impact test logic has on design timing, area, power and congestion. This eliminates time-consuming iterations between RTL synthesis, test and physical implementation, helping designers converge on both test and design goals faster. The test solution is comprised of DFTMAX™ Ultra, DFTMAX and TetraMAX® for power-aware logic test and physical diagnostics; DesignWare® STAR Hierarchical System for IEEE standards-based hierarchical SoC test; DesignWare STAR Memory System® for embedded and external memory test, repair and diagnostics; DesignWare IP for high-speed interfaces with self-test; and Yield Explorer for design-centric yield analysis.
DC Explorer, the newest addition to the Design Compiler Family, enables early RTL and floorplan exploration to accelerate development of high quality RTL and constraints leading to faster synthesis, and place-and-route. The Design Compiler family also includes: the award-winning synthesis-based test solution for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon; Power Compiler™, for low power synthesis and optimization; Formality® for equivalence checking; Synphony C Compiler for high-level synthesis of image processing IP; and the DesignWare® Library with its unequalled variety of synthesizable IP. This best-in-class, production-proven solution is integrated to achieve the industry's fastest and most predictable RTL-to-GDSII flow.