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Sep 22, 2014Users Cite 10 Percent Smaller Design Sizes with Latest Releases of Synopsys' Design Compiler
New Innovations Also Reduce Leakage Power and Accelerate Design Schedules

Jun 03, 2014Synopsys and Intel Collaborate to Enable 14-nm Tri-Gate Design Platform for Use by Customers of Intel Custom Foundry
Extends Production-Proven 22-nm Design Enablement to 14-nm for Cloud Infrastructure and Mobile Market Segments

Jun 02, 2014Samsung and Synopsys Deliver Design Tools and IP for 14-nm FinFET Process
FinFET-ready Silicon-proven Tools and IP Available for Immediate Design of SoCs

May 01, 2014Mellanox Technologies Standardizes on Synopsys' Design Compiler Graphical
Achieves Higher Operating Frequencies and Smaller Area

Apr 30, 2014Synopsys DFTMAX Ultra Deployed By Dialog Semiconductor to Successfully Test Silicon Parts
Delivers 3X Higher Test Compression and Ease-of-Deployment

Apr 28, 2014Centaur Technology Deploys Synopsys' Formality Ultra to Shorten Design Schedules by Weeks
Enables 2X Faster Implementation and Verification of Functional ECOs

Apr 14, 2014TSMC Certifies Synopsys Digital and Custom Solution for V1.0 N16 Process
Certification Enables Designers to Realize the Power, Performance and Area Benefits of FinFET Technology

Jan 29, 2014CEVA Utilizes Synopsys’ Design Compiler Graphical to Achieve Higher Frequency and Smaller Area for its DSP Cores
Expedites CEVA’s Implementation of its DSPs by Simplifying the Back-end Flow with Highly Predictable Results

Jan 28, 2014Fujitsu Semiconductor and Synopsys Deliver an Optimized and Predictable Customized SoC (ASIC) Design Flow
Design Compiler® Early Exploration, Complemented with New Algorithms for Area and Timing Optimization, Improves Design Utilization and Accelerates Time-to-Market

Sep 03, 2013Samsung Widely Deploys Synopsys' Design Compiler Graphical for Mobile SoC Designs
Achieves Area and Power Reduction Critical to Success in the Mobile Market

Feb 28, 2012BiTMICRO Selects Synopsys for Chip Design Automation
Two third-generation SSD controllers taped out using Synopsys' Galaxy Implementation and Discovery Verification Platforms

Feb 09, 2012CSR Selects Synopsys for Advanced-Node SoC Design
Adoption of Synopsys Galaxy Platform Driven by Superior Results for ARM CPU-based SoCs

Dec 14, 2011GUC Achieves Gigahertz+ Frequency on ARM Processor with Synopsys IC Compiler


Dec 14, 2011Synopsys Enables Silicon Success for GLOBALFOUNDRIES First Complex 20-nm Design


Dec 05, 2011Industry Leaders Achieve Significant Power and Performance Gains With Synopsys' Low Power Solution
Industry Leaders Achieve Significant Power and Performance Gains With Synopsys' Low Power Solution Advanced Solution Now in Mainstream Usage with More Than 125 Successful Tapeouts

Oct 18, 2011Synopsys Low Power Solution Accelerates Time to Market for 3G Mobile IC
CYIT Completes Tapeout Five Weeks Ahead of Schedule with First-Pass Silicon Success

Apr 19, 2011Synopsys Design Compiler Graphical Cuts Design Time at Exar
Exar Engineers Detected and Fixed Routing Congestion Hot Spots in Synthesis Before Hand-off to Physical Implementation

Mar 28, 2011Synopsys Unveils DC Explorer for Early RTL Exploration
Solution Accelerates Design Implementation through Early Exploration While Tolerating Incomplete Data

Jan 31, 2011Synopsys Galaxy Implementation Platform Addresses Gigascale Design
Latest Release Includes Scalability, Convergence and Throughput for Large IC Implementation on Advanced Node Technology

Jan 10, 2011Synopsys Speeds Equivalence Checking by 2X at Nuvoton
Productivity Advantage Over Existing Solution Cited as Main Driver to Standardization on Formality

Nov 10, 2010Synthesis-Based Test Technology Increases Designer Productivity
Synopsys’ new test technology enables designers to achieve optimal quality-of-results and eliminate time-consuming iterations between design and test.

Oct 26, 2010Power-Aware Test Speeds Time to Volume Production at Realtek
Reducing Power Consumption and IR Drop During Manufacturing Test Enables Faster Delivery of Working Silicon

Sep 08, 2010Synopsys DFTMAX Compression Cuts Pin-Limited Test Cost by 95 Percent at Silicon Image
Using the new pin-limited test capability in Synopsys’ DFTMAX, Silicon Image designers easily implemented test compression for the mixed-signal chip in just two days, substantially reducing test time, data and cost while achieving high test coverage.

Aug 09, 2010Synopsys Galaxy Implementation Platform Used by TSMC for 28nm Process
Product Qualification Vehicle Test Chip Tapeout Includes Advanced Routing Rules, Low Power and Signoff Capabilities




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