|GUC ASIC Methodology: Higher Predictability and Superior Results with Design Compiler Graphical|
Achieving higher performance, lower power and smaller die size in an efficient timeframe is key for GUC’s ASIC design services. In this webinar, Kazuyuki Irie, Department manager for GUC Japan discusses the challenges of a traditional ASIC design flow that required timing margin in synthesis for faster design closure; leading to less than optimal area and power results. He will discuss how GUC Japan recognized a Design Compiler Graphical based methodology that improves predictability, reduces schedule and achieves superior results for GUC Japan.
Kazuyuki Irie, Department Manager, GUC Japan
Oct 08, 2015
|STMicroelectronics’ Experience: Synopsys Logic BIST for Automotive and Safety-Critical Designs|
ICs targeted for safety-critical applications must be able to perform in-system self-test in compliance with functional safety standards such as ISO 26262. In this webinar, Synopsys highlights synthesis-based logic BIST that addresses the self-test requirements for safety-critical designs. Our guest speaker from STMicroelectronics presents results and details of Synopsys’ test solution successfully deployed on production designs.
Cinzia Bartolommei, Senior DFT Engineer, STMicroelectronics; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Jul 30, 2015
|Advantest and Synopsys: Taking Test Cost Reduction to the Next Level|
In this webinar, we highlight two methodologies, multisite test and concurrent test, that minimize test application time and maximize throughput.
Dave Armstrong, Director of Business Development, Advantest; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Apr 30, 2015
|ARM Perspective: Area Reduction on ARM Mali Cost-Efficient GPUs|
In this joint webinar, ARM describes methodologies, design choices and results achieved by an area-centric reference implementation of the ARM Mali GPU using Design Compiler Graphical and IC Compiler.
Pierre-Alexandre Bou-Ach, Physical Design Lead, ARM; Priti Vijayvargiya, Director of RTL Synthesis Product Marketing,
Apr 23, 2015
|Imagination and Synopsys: Reduce Dynamic Power and Area up to 50% on a GHz+ MIPS Core Implementation|
In this webinar, Imagination Technologies will share how their selection of standard cell architecture and use of several dynamic power techniques available in Design Compiler and IC Compiler helped them achieve optimal power and area savings for their MIPS family of CPU cores.
Maya Mohan, Hardware Design Engineer, Imagination Technologies and Jeffrey Lee, CAE Manager, Power Compiler, Synopsys
Jul 10, 2014
|Achieving Ultra-Low DPPM: Avago Case Study|
Hear experts from Avago and Synopsys describe key advanced fault models available in Synopsys' synthesis-based test solution, DFTMAX and TetraMAX ATPG, to achieve ultra-low DPPM.
Stefano Zanatta, DFT Engineer, Avago Technologies; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Jun 26, 2014
|33% Higher Design Density: Fujitsu’s Customized Flow with Design Compiler|
Learn about Fujitsu’s new Customized SoC (ASIC) handoff flow with early logical and physical collaboration to improve design density, lower power and minimize iterations.
Tatsuya Nakae, Director of SoC Design Methodology Development, Fujitsu; Hitesh Patel, Product Marketing Manager, Synopsys
May 01, 2014
|Dialog Semiconductor and Synopsys Present: New DFTMAX Ultra for Squeezing Out More Test Compression with Fewer Pins|
The demand for pin-limited compression is being driven by tighter form factors, the design of multicore SoCs that require few pins per core for test access, and the adoption of multisite testing as a technique to reduce test application time and cost. In this webinar, we will highlight how Synopsys’ new DFTMAX Ultra is designed from the ground up to achieve high compression using fewer digital scan pins and a minimum of one pair of scan pins. Our guest speaker will then discuss how DFTMAX Ultra is being successfully deployed to lower the cost of testing mixed-signal designs at Dialog Semiconductor.
Richard Illman, Technical Staff Member, Dialog Semiconductor; Carl Holzwarth Corporate Applications Engineering Director, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Apr 17, 2014
|ST and Synopsys Present: Synphony C Compiler for Faster Implementation of Image Processor IP|
Video and image processing hardware has become pervasive in smartphones, cameras, camcorders, autos, security equipment and a host of other devices. As the algorithms often begin in C and C++, high-level synthesis (HLS) from these languages to high-quality RTL can boost design productivity by 5-10X. Our guest speaker will discuss how Synopsys’ Synphony C Compiler HLS solution is being successfully deployed to meet the challenges of designing imaging processors at STMicroelectronics. Learn how you can use Synphony C Compiler and its C++ image processing library to accelerate the delivery of your high-performance image processing IP in a fraction of the time it takes using traditional methods.
Franck Hellard, Principal Engineer, STMicroelectronics; Craig Gleason, CAE Manager, Synopsys; and Chris Allsup, Marketing Manager, Synopsys
Apr 10, 2014
|Qualcomm’s Experience: Getting Superior Results with Design Compiler 2013.12|
Learn how Qualcomm, describes how Qualcomm was able to achieve superior timing, area, and power results while maintaining tight correlation to layout using Design Compiler's latest release 2013.12.
Karl Pfalzer, Implementation Architect, Qualcomm; Priti Vijayvargiya, Director of RTL Synthesis Product Marketing, Synopsys
Feb 26, 2014
|TSMC & Synopsys Present: DFTMAX Compression, IEEE 1500-based Hierarchical Test & iJTAG|
As the complexity of systems-on-chip increases, so does the need to leverage standards-based methodologies to implement test in a hierarchical manner, across multiple cores.
Dr. Saman Adham, Senior Manager, TSMC; Robert Ruiz, Product Marketing Manager, Synopsys; Adam Cron, Principal Engineer, Synopsys
May 23, 2013
|Fujitsu’s Experience: Addressing Large Design Challenges with the latest Design Compiler Technologies|
Increased design size and complexity can lead to exponential growth in turn-around-time (TAT). This webinar describes the methodology Fujitsu developed using DC Explorer and Design Compiler Graphical to achieve faster design convergence and reduced TAT on large, 40 million+ instance designs. You will hear how DC Explorer speeds up the development of high-quality RTL and constraints and generates an early netlist for guiding and optimizing floorplanning. This early floorplan exploration helps identify layout issues and provides more accurate area estimation up-front in the design flow to help create optimal design partitions, with a better starting point for implementation. Learn how Fujitsu then uses Design Compiler Graphical to achieve higher performance and tighter correlation with place and route for faster design convergence.
Koji Inoue, Corporate Application Engineer, Synopsys
Dec 06, 2012
|AMD Perspective: Achieving Superior QoR Faster with the Latest Design Compiler Technologies|
Jack Randall, principal member of the technical staff at AMD, describes his design methodology for implementing a low power, multi-million instance processor core with the latest Design Compiler technologies.
Jack Randall, Principal Member of Technical Staff, AMD; Sandra Ma, Group Director of Corporate Applications, Synopsys
Jun 19, 2012
|Expediting Design Schedules with DC Explorer - Qualcomm’s Experience|
Learn how DC Explorer enables early RTL exploration leading to a better starting point for RTL synthesis and accelerates design implementation.
Matt Baker, Staff Engineer, Qualcomm; Sandra Ma, Sr. Director, Corporate Application Engineer, Synopsys; Liz Chambers, Product Marketing Manager, Synopsys
Nov 01, 2011
|Harness the Power of SystemVerilog with Design Compiler to Increase Productivity|
Learn how the use of SystemVerilog constructs can result in concise, portable RTL that is easier to maintain and consistent with verification requirements.
Liz Chambers, Product Marketing Manager for Design Compiler, Synopsys; James Argraves, Corporate Applications Engineering Manager for HDL Compiler, Synopsys
Apr 27, 2011
|Accelerate your design closure with DC Ultra |
Join this webinar to hear directly from senior product team members on how you can achieve superior results faster utilizing sophisticated optimizations of DC Ultra.
Sandra Ma, Synopsys; Janet Olson, Synopsys
Apr 21, 2009