Implementation & Signoff 

Accelerating Advanced Integrated Circuit Design Innovations  

Physical effects of semiconductors are becoming more and more interrelated. Each design decision can create unintended consequences. In addition to the old problems generated by wire capacitance, engineers can no longer manually balance the myriad effects such as leakage current, inductive noise or IR drop. Manufacturing processes and environmental variation can render your functional chip useless or economically unviable. Market forces are creating demands of higher volumes at lower and lower price points. Investors are losing their appetite for risk and paying a premium for predictable success. Designers must walk a tightrope of price and performance to reach their time-to-market goals.

  • Tools
 

DC Explorer
Early RTL Exploration Accelerates Synthesis and P&R
PDF DOWNLOAD DATASHEET (PDF)


DC Ultra
Best-in-class timing, area and power QoR correlated with physical results
PDF DOWNLOAD DATASHEET (PDF)


Design Compiler Graphical
Extends topographical technology to predict & alleviate routing congestion
PDF DOWNLOAD DATASHEET (PDF)


Power Compiler
Provides complete solution for power synthesis & optimization
PDF DOWNLOAD DATASHEET (PDF)


DFTMAX
Adaptive scan compression for cost-effective DSM testing
PDF DOWNLOAD DATASHEET (PDF)


TetraMAX ATPG
Automatic test pattern generation & diagnostics for high-quality tests
PDF DOWNLOAD DATASHEET (PDF)


DesignWare IP
Reduce Risk and Speed Time-to-Market with High Quality IP


Formality
Comprehensive, fast, intuitive equivalence checking
PDF DOWNLOAD DATASHEET (PDF)


Synphony C Compiler
Synphony C Compiler - High-level synthesis to accelerate design of image processing IP
PDF DOWNLOAD DATASHEET (PDF)


IC Compiler II
A complete place and route system that enables 10X faster throughput for designs across all process nodes.



IC Compiler
IC Compiler is an integral part of the Synopsys Galaxy™ Design Platform that delivers a complete design solution



Talus
Netlist-to-GDSII implementation for designs at or above 28nm


Custom Designer SE
Custom design schematic editor
PDF DOWNLOAD DATASHEET (PDF)


Custom Designer LE
Custom design layout editor
PDF DOWNLOAD DATASHEET (PDF)


Custom Designer SDL
Custom design schematic-driven layout
PDF DOWNLOAD DATASHEET (PDF)


Galaxy Custom Router
Analog and special net routing for custom and digital IC design



Laker Custom Design
Custom IC design and layout solution


Laker Blitz
Chip-level layout editor for chip finishing operations


Laker Flat Panel Display
Flat panel display editor


Laker Test Chip Development
Automated test chip development platform


Helix
Device-level placement for custom IC design
PDF DOWNLOAD DATASHEET (PDF)


PCell Xtreme
Persistent PCells for OpenAccess
PDF DOWNLOAD DATASHEET (PDF)


Titan Accelerators
Options for augmenting mixed-signal design flows


PrimeTime
Golden timing sign-off including STA, SSTA, SI, and power analysis
PDF DOWNLOAD DATASHEET (PDF)


NanoTime
High-performance transistor-level STA for custom design
PDF DOWNLOAD DATASHEET (PDF)


PrimeRail
In-Design Rail Analysis for Place-and-Route Engineers
PDF DOWNLOAD DATASHEET (PDF)


StarRC
Industry leading parasitic extraction for digital and custom design
PDF DOWNLOAD DATASHEET (PDF)


StarRC Custom
Unified gold standard extraction including Rapid3D fast field solver
PDF DOWNLOAD DATASHEET (PDF)


SiliconSmart
Advanced cell characterization
PDF DOWNLOAD DATASHEET (PDF)


Liberty NCX
Reference library characterization system
PDF DOWNLOAD DATASHEET (PDF)


IC Validator
In-design physical verification solution for 45nm and below
PDF DOWNLOAD DATASHEET (PDF)


Hercules
Technology-leading physical verification for 45nm and above


PrimeYield LCC
Accurate, production-proven lithography compliance checking


Synplify Pro
Logic synthesis for FPGA implementation


Synplify Premier
Fast implementation of advanced FPGAs and FPGA-based prototypes


Identify RTL Debugger
Simulator-like visibility into hardware operation


Synphony Model Compiler
Faster, more efficient ASIC & FPGA HW Development for DSP Algorithms



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