|Tapeout of a High-Performance ARM Cortex-A57 Processor-Based Server SoC Using Synopsys Galaxy Design Platform|
In this video, you’ll hear briefly about Synopsys’ participation at ARM TechCon 2014 followed by AMD’’s presentation on the recent tapeout of the AMD OpteronTM A1100 “Seattle” SoC based on ARM's 64-bit ARMv8 architecture.
Manoj Rehani, Director, ASIC Design, AMD
Phillip Young, Principle Member Technical Staff, ASIC Design, AMD
|Efficient Hardening of ARM Cortex-A57/-A53 Processor Subsystems in FD-SOI Process Technology Using Galaxy Design Platform|
In this video, you’ll hear briefly about Synopsys’ participation at ARM TechCon followed by STMicroelectronics sharing its approach to the efficient implementation of ARM® Cortex®-A57/-A53 processor-based system-on-a-chip (SoC) designs.
Arnaud Rayer, Senior Staff Backend Engineer, STMicroelectronics
|The Many Faces of Advanced Technology|
On June 3, 2013, Synopsys hosted an IC Compiler luncheon presentation during the Design Automation Conference (DAC). Attendees heard from industry experts in foundry, processor, wireless and consumer electronics companies, such as Oticon, Qualcomm, Samsung and STMicroelectronics that while “advanced” can have multiple facets, advanced design of any color is being done with IC Compiler. This video gives you a chance to hear from these advanced designers themselves.
Michael Jackson, Synopsys; Mamta Bansal, Qualcomm; Lars Kvisgaard Hansen, Oticon; Domenico Genova, STMicroelectronics; Kee Sup Kim, Samsung (live presentation only)
|Achieving Optimum Results on High-Performance Processor Cores|
This video was taken during Synopsys’ User Group (SNUG) in Silicon Valley on March 25, 2013, where attendees had the opportunity to hear from a panel of designers, with hands-on experience, share their insights and best practices for achieving optimum results on high-performance processor cores.
Brian Millar, ShiChin Ouyang, Frédéric NYER
|Leading the Way to 20nm Design with IC Compiler|
On June 4, 2012, Synopsys hosted an IC Compiler luncheon presentation during the Design Automation Conference (DAC).
Attendees heard from industry experts in foundry, processor, wireless and consumer electronics companies, such as GLOBALFOUNDRIES, Oracle, Samsung and STMicroelectronics who shared how they have successfully met the 20nm design enablement challenge using IC Compiler. This video gives you a chance to hear from the trail blazers themselves!
|Achieve Gigahertz+ Performance on ARM® Cortex™-A15 Processor |
This videotaped session was jointly delivered by Synopsys and HiSilicon Technologies at ARM TechCon 2012. Synopsys’ Kevin Yip highlighted Synopsys’ high-performance core methodology and key technologies in Design Compiler®, IC Compiler™, PrimeTime® and IC Validator. Featured technologies included physical guidance for implementation predictability, multisource clock tree synthesis for an OCV tolerant clock structure, transparent interface optimization for top-level closure and final stage leakage recovery for leakage power optimization. Chunsheng Liu of HiSilicon Technologies shared HiSilicon’s experience and results on the successful application of these performance and power enabling techniques in the tapeout of a complex ARM Cortex-A15 based SoC design.
Kevin Yip, Senior Applications Consulting (AC) Manager, Synopsys Inc.
Catherine Xiayu, Director of the COT Design Department, HiSilicon Technologies
Chunsheng Liu, Principle Engineer in the COT Design Department, HiSilicon Technologies
|Optimized Implementation of A Gigahertz+ ARM® Cortex™-A15 Processor|
This presentation was delivered by Brian Millar of Samsung at ARM TechCon 2012. Mr. Millar describes how the Synopsys Galaxy™ Implementation Platform was used for a high performance, low power implementation of an ARM® Cortex™-A15 processor for mobile applications. The successful application and trade-offs of key technologies and techniques from synthesis to place and route that enabled high performance were described. Technologies highlighted include topographical synthesis, physical datapath, clock mesh, multivoltage design, and multicorner/multimode optimization, all of which were used successfully by the design team to achieve the aggressive performance/power target and an improvement of 20 percent over traditional implementation techniques.
Brian Millar, Physical Implementation Lead, Samsung Electronics
|High-Performance Physical Design of a 28nm Quad-Core ARM® Cortex™-A15 Processor|
This presentation was delivered by Jason Karka and Michael Robinson of Texas Instruments at Austin SNUG 2012. It highlights key strategies used in a Synopsys IC Compiler™ place-and-route flow for a 28nm quad-core ARM® Cortex™-A15 processor with 4MB L2 Cache. Various physical design techniques were used to obtain very high clock frequencies. Many of these tactics will be of use not only to designers implementing quad-core A15 processors, but also to those designing other 28nm high-performance chips. Topics discussed include net patterning and layer assignment to deal with a tapered metal stack, hierarchical partitioning, placement density and clustering, clock gate cloning, useful skew, logic-level balanced CTS and techniques for post-route setup and hold closure.
Jason Karka, Texas Instruments Designer
Michael Robinson, Texas Instruments Designer
|Enabling Gigascale Design with IC Compiler|
During DAC 2011, Synopsys hosted the IC Compiler Gigascale Design luncheon event in San Diego, CA. IC Compiler, a key component of the Galaxy Implementation platform, is the leading physical implementation solution on the market today. Hear from your peers at leading consumer and networking companies, such as Lantiq, LSI, Juniper Networks, Panasonic and Renesas who have successfully taped out multi-million instance, gigascale designs with IC Compiler.
Antun Domic, IC Compiler Luncheon Event Moderator, Sr. Vice President & General Manager, Implementation Group, Synopsys, Inc. -- JC Parker, Senior Director of Design Tools and Methodologies, LSI Corporation -- Deepak Lall, Sr. ASIC Manager, Juniper Networks -- Tomokazu Ito, Back–End Design Technology, Development Engineer, Renesas -- Hiromasa Fukazawa, Senior Engineer, Panasonic -- Dirk Claussen CAD – Senior Specialist, Lantiq
|PrimeTime SIG at DAC 2012 |
A PrimeTime SIG event was held in San Francisco during DAC on Monday, June 4, 2012. One hundred and eighty PrimeTime users and managers attended the event from more than sixty eight semiconductor companies. The theme of this SIG was Next-generation Hierarchical Timing Technology — HyperScale. Eighteen Ecosystem Partners, along with PrimeTime R&D, participated and interacted with attendees.
|PrimeTime SIG at DATE 2012 |
A PrimeTime Special Interest Group (SIG) event on Gigascale design signoff featuring Advanced OCV, PrimeTime ECO, and HyperScale technology was held at DATE in Dresden, Germany, on Tuesday, March 13, 2012. The event was held over lunch where PrimeTime users and managers from semiconductor companies had the opportunity to talk with industry peers and PrimeTime R&D.
|Design Challenges and Solutions for High-Performance Mobile SoCs |
Samsung Electronics discussed design challenges and solutions for high-performance mobile SoCs during the Synopsys High-Performance Insight Series at DAC 2012.
In this video, Dr. Seomun describes Samsung’s success using the Galaxy™ Implementation Platform on its latest cutting-edge designs.
Jun Seomun, Ph.D. Sr. Engineer, Design Technology Team, Infrastructure Design Center, Samsung Electronics, System LSI
|High-Performance Design on Galaxy Implementation Platform |
During the Synopsys High-Performance Insight Series at DAC 2012, NVIDIA’s Vikas Agrawal discusses NVIDIA’s success designing for high performance using the Galaxy™ Implementation Platform on its latest designs.
VLSI Design Methodology Manager, NVIDIA
|DAC 2010 IC Compiler In-Design Videolog|
At DAC in June 2010, industry experts at AMD, LSI Corporation, Renesas Electronics, Samsung, STMicroelectronics and Texas Instruments presented to over 200 Synopsys guests. The presenters explained how they relied on In-design physical verification with IC Validator for improved productivity and faster design closure.