|Eliminating Late-Stage DRC Surprises with In-Design Physical Verification|
Third in the In-Design technology series featuring several high productivity in-design physical verification flows with IC Validator, including Automatic DRC Repair and Pre-Routing Verification – all from within IC Compiler.
Kerstin McKay, CAE Director, Physical Verification, Synopsys
May 05, 2010
|In-Design for Faster Design Closure|
First in a series addressing 32/28nm sign-off bottleneck challenges and the solutions best suited to mitigate these challenges. Learn how Synopsys’ In-Design solutions make it possible for place-and-route engineers to accelerate design closure by enabling signoff analysis from within the implementation flow.
Dan Page, Vice President of R&D, Implementation Group, Synopsys
Mar 02, 2010