Webinars 

TSMC and Synopsys: 10nm Physical Verification Enablement for IC Validator
Learn about TSMC’s 10nm design enablement readiness & the tooling supported in their physical design flow; Synopsys will cover new technologies addressing the challenges of 10nm design verification.
Captain Liu, Manager, Design Methodology and Service Marketing TSMC; Ron Duncan, Sr. CAE Manager, Synopsys
Mar 03, 2016
 
UMC and Synopsys: A Complete and Differentiated 28nm Signoff and Manufacturing Infrastructure – Traditional Chinese
This webinar covers the benefits of In-Design, an integrated methodology enabling you to run foundry signoff DRC and Metal Fill runsets inside the place-and-route environment, as UMC and Synopsys share their proven design flow for 28nm chip design.
Anderson Huang, UMC; Dr. Daw Hsu, Synopsys
Oct 09, 2014
 
UMC and Synopsys: A Complete and Differentiated 28nm Signoff and Manufacturing Infrastructure – Simplified Chinese
This webinar covers the benefits of In-Design, an integrated methodology enabling you to run foundry signoff DRC and Metal Fill runsets inside the place-and-route environment, as UMC and Synopsys share their proven design flow for 28nm chip design.
Anderson Huang, UMC; Dr. Daw Hsu, Synopsys
Oct 09, 2014
 
UMC and Synopsys: A Complete and Differentiated 28nm Signoff and Manufacturing Infrastructure
This webinar covers the benefits of In-Design, an integrated methodology enabling you to run foundry signoff DRC and Metal Fill runsets inside the place-and-route environment, as UMC and Synopsys share their proven design flow for 28nm chip design.
Anderson Huang, UMC; Dr. Daw Hsu, Synopsys
Sep 25, 2014
 
Latest Advances in PrimeRail In-Design Vector Free Rail Analysis
See the latest innovations in PrimeRail's In-Design solution including rail integrity and static/dynamic analysis that enable designers to achieve significant productivity in advanced node designs.
Jason Binney, Principle CAE, Synopsys
May 14, 2014
 


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