- Designers of large FPGAs are faced with tight deadlines and budgets, making it critical that they find ways to improve productivity. FPGAs used for FPGA-based prototyping as well as production deployment are incurring synthesis runtimes that range from several hours to an entire day for the most aggressive designs. The latest version of Synopsys' Synplify® Premier FPGA design tool significantly improves turnaround time with the following:
- Hierarchical design capabilities
- Automated multiprocessing
- Continue-on-Error (CoE)
- Faster synthesis runtime modes and algorithms
Hierarchical capabilities enable a "divide-and-conquer" design and debug approach with incremental features to improve and fix specific parts of the design. The hierarchical design environment allows engineers and design teams to develop blocks in parallel on multiple servers, update and improve targeted parts of the design while preserving others that already work, synchronize and integrate changes and reuse design modules and IP more efficiently. Designers can export modules that are being improved as self-contained sub-projects that include everything needed to work on the block in isolation, including TCL scripts, synthesis files and reports. Incremental synthesis and incremental place-and-route (P&R) flows are available to update those portions of the design that have been modified, reducing both synthesis and P&R runtime by half or more.
To speed the turnaround time during the debug and modify phase of a multi-FPGA ASIC prototyping project, the hierarchical design features of Synplify can be applied in the context of a project managed by Synopsys' Certify software. After the partitioning phase when SoC design blocks are distributed across devices, each source-level partition (SLP) project can be further divided into multiple synthesis sub-projects that can be executed in parallel for faster turnaround time as subsections are debugged and modified.
Multiprocessing with Synplify Automatic Compile Points (ACP) technology performs automatic design partitioning of the design so that parallel synthesis of large designs can occur automatically and incrementally leveraging multi-processor systems. On very large designs, results show that 30% faster runtimes with no degradation in quality of results (QoR) are typical when using two-CPU multiprocessing and even more runtime savings are available with four CPU multiprocessing. When multiprocessing and ACP are used in conjunction with Synplify Premier software's fast synthesis mode, synthesis runtime can be improved by up to 10X.
Multiprocessing is also available for use with manually-created RTL partitions, called compile points, for block-based and incremental design flows. Compile points for each block are synthesized in parallel, affording additional runtime savings.
Multi-FPGA ASIC prototyping projects managed by Certify software also see improved synthesis throughput of each SLP project's output with ACP.
Continue-on-Error, a feature of the Synplify Premier software, reduces the number of iterations required to identify non-syntax related compiler issues. By reducing the number of iterations, CoE significantly shortens the overall time required to get the design successfully synthesized and a working implementation created on the board. CoE creates a consolidated report of the errors and generates an RTL view of the design with error modules highlighted to enable the user to quickly pinpoint design issues and erroneous modules. Users can then complete synthesis either by fixing all design issues or by manually black-boxing erroneous modules and then merging fixed modules back into the synthesized netlist eliminating numerous design iterations.
Applying CoE with the Certify tool it is especially useful during the design migration phase of a multi-FPGA prototype project where it is common that the prototype engineer implementing the design in an FPGA may not be familiar with the ASIC RTL code and the number of errors encountered during initial synthesis may be significant. CoE makes the import of potentially thousands of design files far more efficient by reducing the number of iterations through the HDL compiler.
Figure 1: Continue-on-Error feature means fewer synthesis iterations when introducing new RTL
Fast Synthesis Algorithms
Synthesis tool performance and fast runtimes are critical when attempting to complete your design on schedule. The Synplify Premier tool leads the industry in fast synthesis runtimes, in the 2012.03 release delivering an additional 30% raw runtime improvement for Altera and Xilinx designs. In addition to these fast runtimes, Synplify Premier software offers users the option to run synthesis even faster, using a fast-mode switch that trades off some performance quality of results for 3x faster runtime. This mode can be used to quickly implement an initial implementation of the design or design prototype on the board so that system testing and system software development and porting can start.
For more information:
The Great Divide: Why Next-Generation FPGA Designs will be Hierarchical and Team-Based (White Paper)
Incorporating hierarchical team-based design is now seen as mission-critical to any company involved in the creation of one of today's high-end FPGA designs. This paper discusses the evolution of FPGAs and FPGA design, the concepts of top-down and divide-and-conquer design flows and the considerations and capabilities required to support true hierarchical team-based design along with content management and design reuse considerations.
Lean how to use "divide and conquer" hierarchical approaches for parallel machine execution or team-based design, and how to develop, tweak and debug your FPGA design efficiently.
Angela Sutton, Staff Product Marketing Manager, FPGA Implementation, Synopsys
Sep 20, 2011
FPGA Design Methods for Fast Turn Around (White Paper)
This white paper takes an in depth look at a variety of techniques to help you speed up your synthesis iterations. Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.