Are your FPGA projects taking too long? Now that FPGA devices have grown into hugely capable Programmable SoC's in their own right, have design methods struggled to keep up? Do you see the forthcoming 40nm devices as a leap too far for your current design methodology?
Help is at hand from Synopsys
In this concise series of three technical webinars presented by the Synplicity Business Group (SBG) you can learn how FPGA Design can be made more productive and predictable.
FPGA designers can always beat their ASIC-using colleagues to a working design in silicon but most manage without a system-level model, a timing closure methodology or a verification strategy. The risk in cutting these corners has usually been balanced against the reward of getting the design to market more quickly. Leading-edge FPGA users have realized that the risk-reward ratio is no longer scalable. They are adopting more powerful, more productive and more predictable design and verification techniques.
This three part on-demand webcast series will introduce Synopsys tools for serious FPGA users, including model-based algorithmic design, IP integration tools, tightly coupled constraint and analysis environments, integrated synthesis and placement, and on-board assertion-based verification linked to RTL simulation.
- To register:
- Click on the hyperlinks above
- Click Enroll
- On the registration form, enter your information and click Submit
- If you would like to attend multiple sessions, you will need to complete a separate registration form for each event.