Synplify Pro and Premier
The Synplify synthesis tools provide fast runtime, performance, area optimization for cost and power reduction, multi-FPGA vendor support, incremental and team-design capabilities for faster FPGA design development.

The Certify prototyping software is a user-friendly tool that works directly from your RTL source code and ASIC IP. Certify software is tightly integrated with the Synopsys HAPS® Family of FPGA-based prototyping hardware or can be deployed as a front-end for custom prototype systems.

The Identify product is a powerful FPGA verification tool that allows you to quickly find and correct functional design errors in hardware at system speed. The Identify software offers advanced triggering capability so you can focus precisely on the design portion you wish to view, at the time you choose to see it. Most importantly, there’s no additional effort required to interpret the results. You add the probes to instrument the design and observe the results directly in your RTL source code.

Synphony C Compiler
Synphony C Compiler reduces development time and cost by shifting the focus of hardware implementation from designing at the RTL level to designing at the algorithmic level. Designers describe hardware in algorithmic C/C++, using Synphony C Compiler to fine-tune the architecture for tradeoffs in performance, power, and area, and generate highly optimized RTL implementations for ASIC or FPGA.

Synphony Model Compiler
Synphony Model Compiler solution provides an easy and automated way to create ASIC and FPGA hardware from high-level models created in the Simulink and MATLAB® model-based environment.

FPGA Design Solution for High-Reliability Applications
Synopsys’ offers a high-reliability solution to help FPGA designers create products that are resistant to radiation-induced errors and single bit glitches. Synplify Premier automates the process of creating special error detection and correction circuitry, which enables a reproducible, requirements-driven design process from system specification and RTL coding to logic synthesis, verification and the final netlist.

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