Synopsys Synplify FPGA Design Tools are an Essential Element for Today's High Reliability Designs
Historically, immunity to soft errors was only considered a requirement for military and aerospace applications that are prone to radiation effects resulting in single-event upsets (SEUs). Today however, even ground level applications are suffering a greater numbers of radiation effects as FPGA process technologies advance. Critical functions such as those for industrial control, high-reliability communications and collision avoidance systems in automotive applications can benefit from automated built-in protection against soft errors.
Synplify® Premier software has built-in safety features, including triple modular redundancy (TMR) and fault-tolerant Finite State Machine (FSM) implementation, to help mitigate SEUs and achieve greater design reliability.
Figure 1: TMR helps mitigate SEUs induced by radiation effects by inserting redundancy during synthesis with triplicated circuitry + voting logic | TMR inserts redundancy by triplicating all or part of the logic in a circuit and then adds in "voting" logic to determine the best 2 out of 3 results in case a signal is changed due to an SEU. With Synplify you can identify where you want redundancy and the tool will automatically apply it.
Error correcting code (ECC) memories can be used to detect and correct single-bit errors. Once you specify in the RTL or constraints file which memory functions are safety critical for your design, the Synplify Premier software infers the ECC memories offered by many FPGA vendors and automatically makes the proper connections. |
Safe FSM implementation involves using error detection circuitry to force a state machine into a reset state or into a user-defined error state so the error can be handled in a specific way. The Synplify Synthesis tools automatically add error detection and mitigation circuitry to identify errors and return the FSM into a safe state in a manner that you specify.
Fault-tolerant FSMs with Hamming-3 encoding can be used to detect and correct single bit errors with a Hamming distance of 3, ensuring that a state register erroneously reaching an adjacent state would be detected and correct operation of the FSM continues.
Be sure to check out the following for more information on using FPGA design tools for high-reliability applications:
High-Reliability Design for FPGAs - SEU Mitigation (Chalk Talk)
Join Amelia Dalton from TechFocus Media and Jeff Garrison, Director FPGA Marketing from Synopsys as they discuss how Single Event Upsets (SEUs) can affect today’s high-reliability systems on the ground as well as in space and how using the right FPGA design tools can help you build designs resistant to those "pesky SEUs".
No Room for Error: Creating Highly Reliable, High-Availability FPGA Designs (White Paper)
Designers of FPGAs for military and aerospace applications need to increase the reliability and availability of their designs. This is particularly true in the case of mission-critical and safety-critical electronic systems. This paper provides brief definitions of key concepts: mission-critical, safety-critical, high-reliability, and high-availability. It then considers the various elements associated with the creation of high-reliability and high-availability FPGA designs including: FPGA design and verification flows, methodologies, processes and standards, architectural and algorithmic exploration, geographically distributed design teams, IP selection and verification, DO-254 compliance and much more.
Angela Sutton, Staff Product Marketing Manager, Synopsys
Faster, Safer Implementation of High-Reliability, High-Availability Designs using FPGAs (Webinar)
Learn techniques on how to build high operation reliability into your FPGA designs in the face of radiation-induced errors in the field, and how to validate and trace the end result of your design implementation before you deploy your FPGA-based system.
Angela Sutton, Staff Product Marketing Manager, FPGA Implementation