High-Reliability Design: No Room for Error 

Synopsys Synplify® Premier Design Software provides an essential element in automating today's high-reliability designs

Historically, immunity to soft errors was only considered a requirement for military and aerospace applications that are prone to radiation effects resulting in single-event upsets (SEUs). Today however, even ground-level applications are suffering a greater number of radiation effects as FPGA process technologies advance. Critical functions such as those for industrial control, high-reliability communications and collision avoidance systems in automotive applications can benefit from automated built-in protection against soft errors.

To learn more about Synopsys' Design for High-Reliability Solutions visit the Synopsys Mil/Aero Solution page. Also available is the Mil-Aero Technical Bulletin, a publication for engineers and their management, dedicated to covering the latest methods for addressing the design and verification challenges of high-reliability aerospace and defense systems.

Try Synplify® Premier software FREESynplify® Premier software has built-in safety features to help mitigate SEUs and achieve greater design reliability.

High-Reliability Design

Figure 1: TMR helps mitigate SEUs induced by radiation effects by inserting redundancy during synthesis with triplicated circuitry + voting logic
  • Triple modular redundancy (TMR) inserts redundancy by triplicating all or part of the logic in a circuit and then adds in "voting" logic to determine the best 2 out of 3 results.
  • Error correcting code (ECC) memory inference for detecting and correcting single-bit errors.
  • Safe FSM implementation to force a state machine into a reset state or into a user-defined error state so the error can be handled in a specific way.
  • Fault-tolerant FSMs with Hamming-3 encoding for detecting and correcting single-bit errors with a Hamming distance of 3, ensuring that a state register erroneously reaching an adjacent state would be detected and correct operation of the FSM continues.
  • Duplicate with compare employs a dual-mode redundancy scheme followed by a comparator circuit to create an ERROR_FLAG signal that alerts to the presence of an SEU, so that the error can be tapped or corrected.

High-Reliability Design

Figure 2: Duplicate-with-compare circuitry can be used to flag errors or to trigger custom error mitigation or scrubbing

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