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FPGA Implementation
FPGA Synthesis
FPGA Platform Support
FPGA Products OS Platform Support
Synplify
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Synphony Model
Compiler*
Windows XP Pro
Windows Vista
Not supported
Not supported
Not supported
Windows 7
64-bit only
RHEL 4 (RedHat Enterprise Linux)
RHEL 5 (RedHat Enterprise Linux)
RHEL 6 (RedHat Enterprise Linux)
64-bit only
64-bit only
64-bit only
SLES 10 (SUSE Linux Enterprise Server)
SLES 11 (SUSE Linux Enterprise Server)
indicates support for both 32 and 64-bit versions of the OS
Minimum Hardware Requirements:
CPU 2Ghz or better, multi-core recommended
RAM 2Gb (16Gb recommended for large designs)
HDD 5Gb free space (100Gb recommended for large designs)
*
See additional requirements for Synphony Model Compiler
ARTICLE
Creating Highly Reliable FPGA Designs
Debug Webinar
10 Ways to Debug your FPGA Design
NEWS RELEASE
Latest Release of Synplify Software Cuts Days off FPGA Implementation Time
ARTICLE
Bugs Be Gone! Smarter debug and synthesis techniques to get your FPGA design to work on the board
FREE PRODUCT EVALUATION
Download a free evaluation of Synplify Pro Logic Synthesis for FPGA Implementation
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News
Latest Release of Synplify Software Cuts Days off FPGA Implementation Time
Latest Synplify FPGA Synthesis Software Offers New High-Reliability Features....
Synopsys Enhances Synplify FPGA Synthesis Software to Enable Higher Reliability....
Synopsys and Achronix Announce Multi-Year Renewal of Synthesis Partnership
Xilinx Announces FPGA Synthesis Support for Xilinx's Newest ISE Design Suite 13
Synopsys and Actel Renew OEM Relationship for FPGA Design Software
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All Synopsys News
Articles
Creating Highly Reliable FPGA Designs
Bugs Be Gone! Smarter debug and synthesis techniques to get your FPGA design to work on the board
Next-Generation Xilinx FPGA Flows
Time is Money! A quick fix for those pesky FPGA design errors
Completing Hardware Innovation Cycles in Less than Six Months: An Internet Data Center Server Case Study
FPGA Design: From Top-down to Bottom-up
Better FPGAs, Sooner
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Datasheets
Synplify Premier
Synplify Pro
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Success Stories
Signalcrafters Achieves Design Goals and Cuts FPGA Cost by 50%
Faraday Technology Corporation Achieves Over 50% Performance Improvement on PCIe Controller Designs with Synplify
IMEC Surpasses Critical Performance Goal for C-Programmable
SeaMicro – Synplify Pro Enables First Time Success
STMicroelectronics Uses Synplify Premier to Quickly Obtain a High-Performance FPGA-Based Prototype
Teradici – ASIC Prototyping Made Fast and Efficient with Synplify Premier
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White Papers
10 Ways to Effectively Debug your FPGA Design
FPGA Design Methods for Fast Turn Around
No Room for Error: Creating Highly Reliable, High-Availability FPGA Designs
The Great Divide: Why Next-Generation FPGA Designs will be Hierarchical and Team-Based
Fast, Efficient RTL Debug for Programmable Logic Designs
Beyond Physical: Solving High-end FPGA Design Challenges
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Webinars
Custom Layout Using the Laker Custom IC Solution
Verilog-to-Verilog Equivalence Checking Using ESP
Samsung and Synopsys share their perspective on 14-nm FinFET design
TSMC and Synopsys Present: DFTMAX Compression, Hierarchical Test and iJTAG
Transaction Debug with Verdi3
Discovery-AMS for Mixed-Signal Verification
Conquering HSPA+ Modem Design
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