|Accelerated Layout for Analog/Mixed-Signal in Nanometer SoCs|
A much more accelerated approach for creating and integrating analog/mixed-signal functions in SoC designs is possible using automated methods to reduce the total effort needed, enable layout to proceed concurrently with circuit design, and typically produce more optimal layouts—especially for smaller die sizes.
Lyndon Lim, Synopsys
|Custom and Mixed-Signal Design Solution|
Synopsys’ unified solution for custom and cell-based design and verification provides a comprehensive, highly integrated suite of tools for advanced-node mixed-signal SoC design. The high degree of integration and interoperability shortens time-to-tapeout and improves design quality.
|Unified Implementation Solution for Digital and Custom SoC Designs|
The Galaxy Implementation Platform provides seamless integration between the IC Compiler physical implementation
and Galaxy Custom Designer custom implementation solutions, accelerating the design development cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development while maintaining design data integrity.
|Understand and Avoid Electromigration (EM) & IR-drop in Custom IP Blocks|
This whitepaper discusses the various trends exacerbating EM and IR-drop effects as well as design and analysis techniques to avoid them, and introduce Synopsys’ transistor-level analysis solution, which includes CustomSim for FastSPICE circuit simulation, StarRC for extraction, and Galaxy Custom Designer for custom layout.
Bradley Geden, Solutions Architect, Synopsys
|Automated Regression for Mixed-Signal Verification|
CustomExplorer™ Ultra represents the next generation in mixed-signal verification environment, including regression management, debug and analysis for complex SoC design.
Duncan McDonald, Product Marketing Manager, Synopsys
|De-risking Variation-aware Custom IC Design with Solido Variation Designer and Synopsys HSPICE|
Challenges in a traditional custom IC variation-aware design flow lead to schedule, product yield, and product quality risks. Solido Variation Designer and Synopsys HSPICE together enable fast and accurate variation-aware design methods that can reduce or remove risks associated with traditional variation-aware design. Together, these tools and methods help to reliably deliver products on schedule that are competitive and cost-effective.
Jeff Dyck, Director of Product Development, Solido Design Automation, Inc.; Kishore Singhal, Scientist, Synopsys
|IC Validator: Physical Verification for Analog Designs|
Physical verification challenges of analog designs are different than the challenges of large digital designs. In addition to complex runset requirements, a tight interface to a parasitic extraction tool and an easy-to-use GUI are needed to use a runset effectively in an analog design environment. IC Validator, the latest generation physical verification tool, can be used to solve these issues. This paper addresses many of the physical verification requirements of analog designers and how they are met with IC Validator.
Al Blais, Global Technology Services
|Accelerating Analog Simulation with HSPICE Precision Parallel Technology|
HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other full mixed-signal circuits. HPP addresses the traditional bottleneck in accelerating SPICE on multicore CPUs with new algorithms that enable a larger percentage of the simulation to be parallelized, with no compromise in golden HSPICE accuracy. Additionally, efficient memory management allows simulation of
post-layout circuits larger than 10 million elements.
Robert Daniels, Sr. Staff Engineer, Synopsys Inc.; Harald Von Sosen, Principal Engineer, Synopsys Inc.; Hany Elhak, Product Marketing Manager, Synopsys Inc.
|SmartDRD Automated DRC Visualization and Correction|
SmartDRD is a new, innovative technology built into Galaxy Custom Designer™ Layout Editor (LE) for interactive DRC violation visualization, detection and correction, commonly known as design-rule-driven (DRD) editing
|Architecting for Productivity in Custom Design|
Advances in modern-era user interface and software design techniques have taken root in custom
design EDA tools, leading to a new potential for huge productivity savings and faster time-to-results.
This white paper explores these techniques as applied to the creative processes of custom and analog
design, including industry-recognized use models, advanced techniques in user interface, open language
programmable cells and extraction for post-layout simulation.
Les Spruiell and
|Extraction techniques for High-performance, High-capacity Simulation |
Today’s advanced process technologies and faster time-to-market schedules are pushing the limits of verification tools. Post-layout simulation runtimes are increasing 2-4x with every new process generation as chip transistor counts double and new parasitic effects come into play. The Synopsys StarRC™ extraction solution offers a wide range of features to boost the simulation performance and capacity of transistor-level custom digital, analog/mixed-signal and memory designs.
Omar Shah, Corporate Application Engineer; Shekhar Kapoor, Marketing Manager
|Multicorner-Multimode – A Necessary and Manageable Reality of Design |
Resolving correlation issues is a time consuming step and is all the more challenging when it has to be done across multiple corners and modes. Tight correlation to signoff is critical for faster time to results.
Ashwini Mulgaonkar, Synopsys Implementation Group
|Physical Datapath - Improved Productivity for All Designs |
Currently, most EDA tools do not provide a solution that addresses the limitations of a custom datapath flow. This paper discusses datapath designs, benefits, limitations, and the use of an automated datapath design capability that allows both custom and ASIC designers to meet aggressive design objectives with ever-tighter project deadlines.
Jafar Safdar, Synopsys Implementation Group
|Realizing Low Power IC Design|
There are numerous techniques to achieve a low-power design and several approaches to structuring the flow. As a starting point, high performance designs require a benchmark proven low-skew, low-insertion delay CTS solution. Correlation to industry standard sign-off engines for accuracy and minimum data format translations are required to achieve fast design closure. The optimal solution includes complete low power capability throughout the design flow. This paper addresses low power design issues and includes technologies and techniques to achieve high performance, low power design goals.
Harvey Toyama, Synopsys Implementation Group
|Reverse Process Migration from 65nm to 130nm in Under Three Months|
Normally, a design team will tackle a new project on a new, smaller-geometry process and realize the benefits of increased performance and lower cost per chip. This white paper addresses the reverse of this situation, in which a functioning 65nm analog and mixed-signal design is “blown up” to a 130nm process to help mitigate the higher mask costs of the smaller geometry.
Bob Lefferts, R&D Group Director, Analog and Mixed-signal IP, Synopsys; Neel Gopalan, AMS CAE, Synopsys
|Accelerating Physical Verification with an In-Design Flow|
There is a growing need for a concurrent physical design and physical verification flow, also known as an in-design physical verification flow. This flow improves the overall turnaround time and ease of use of the physical verification process. This paper provides a production-proven example of this flow.