|Eliminate DDR3 Timing Errors with HSPICE and Zuken Constraint-based PCB Routing|
Learn how to analyze signal integrity of critical traces in your PC board layout, incorporate board parasitics and define design constraints to eliminate timing violations.
Griff Derryberry, Applications Engineer, Zuken USA; Hany Elhak, Product Marketing Manager, Synopsys
Dec 11, 2013
|Power Management ICs – Efficient Design: A Richtek and Synopsys Perspective|
Richtek and Synopsys present the key challenges and trends with latest power management Integrated Circuits and discuss recent EDA tool innovations to shorten development time and maximize QoR.
K C Chang, Vice President, Technology Development, Richtek Technology Company; Andy Biddle, Solution Marketing Manager, Synopsys
Oct 03, 2013
|Advanced-node Custom Layout Using the Laker Custom IC Solution|
Learn about Laker’s rule-based layout, schematic-driven layout, and pattern-based multi-device layout features--ideal solutions for those seeking to improve custom layout productivity at 20-nm and below.
Neel Gopalin, Corporate Applications Engineer, Synopsys; Christopher Shaw, Senior Staff Technical Marketing Manager, Synopsys
May 30, 2013
|Accelerate Time-to-Tapeout with IC Compiler Custom Co-Design|
Learn how using IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development.
Christopher Shaw, Senior Staff Technical Marketing Manager, Synopsys; Randy Bishop, Principal Engineer, Synopsys
Oct 24, 2012
|High-Productivity Analog Verification and Debug with CustomSim and CustomExplorer Ultra|
See how Synopsys' advanced analog verification solution can dramatically increase your verification productivity with CustomExplorer Ultra, along with CustomSim and CustomSim-VCS.
Duncan McDonald, Product Marketing Manager, Synopsys
Jul 11, 2012
|Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks|
Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.
Bradley Geden, Solution Architect, Synopsys
Oct 26, 2011
|Use IC Compiler and Custom Designer to Shave Weeks Off Your SoC Development Cycle|
Learn how the seamless integration between IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits at any stage of development.
Chris Shaw, Sr. Technical Marketing Manager, Synopsys;
Denis Goinard, CAE Manager, Synopsys
Oct 19, 2011
|Eliminating Late-Stage DRC Surprises with In-Design Physical Verification|
Third in the In-Design technology series featuring several high productivity in-design physical verification flows with IC Validator, including Automatic DRC Repair and Pre-Routing Verification – all from within IC Compiler.
Kerstin McKay, CAE Director, Physical Verification, Synopsys
May 05, 2010
|Custom Designer: Advances in Custom Layout Automation with SmartDRD|
SmartDRD technology visualizes, prevents and automatically fixes DRC violations to help designers quickly achieve DRC clean designs with significantly reduced effort.
Marc Swinnen, Sr. Product Marketing Manager, Synopsys; Christopher Shaw, Technical Marketing Manager, Synopsys
Mar 23, 2010
|HSPICE/Custom Designer for Analog & RF Circuit Design|
Analog/RF design solution helps meet design challenges
Christopher Labrecque, HSPICE Marketing Manager, Synopsys; Fredrik Ivarsson, Custom Design Corporate Applications Engineer, Synopsys
Nov 05, 2009
|Front-to-Back AMS Flow using Custom Designer|
Follow the front-to-back development of an AMS block using Synopsys' Galaxy Custom Designer implementation solution.
Joe Mastroianni, VP of R&D, Les Spruiell, Product Marketing Manager, Synopsys; Chris Shaw, Technical Marketing Manager, Synopsys
Nov 03, 2009