Galaxy Custom Designer® LE is the modern-era choice for layout entry and editing, enabling users to meet the challenges of today’s fast-moving nanometer designs. With little or no learning curve, layout editing tasks with Custom Designer are accomplished with fewer clicks, quicker menu access, and less pop-up menu clutter.
Architected from the ground up with maximum productivity in mind, Custom Designer LE enables ultra-fast layout editing with advanced P-cell support and timesaving layout automation through capabilities like intelligent multipart paths that maintain DRC correctness.
“With Custom Designer you can immediately be more productive if you are familiar with old-school layout systems."
-Andrew Bosik, Senior Analog Mask Designer
An integral component of the full custom design system, Custom Designer LE provides block- and transistor-level layout and editing capabilities in a unified platform for both cell-based and mixed-signal custom content.
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- Key Benefits
- One unified platform for both cellbased and custom content speeds complex chip design and integration tasks
- Supports Synopsys’ IC Validator, Hercules™ DRC/LVS and StarRC™ flows for industry signoff physical verification
- Supports the IPL Alliance’s Interoperable PDK (iPDK) libraries for industry-wide design data sharing
- Provides multiple-layer purpose-pair browsers in a single session when editing designs in multiple libraries
- Powerful, interactive layout automation tools accelerate design completion through near-DRC clean layout, making post-DRC fixing a trivial task
Figure 1: Custom Designer LE’s familiar look-and-feel immediately boosts designer productivity
Extending the Galaxy Implementation Platform
As semiconductor designs demand more custom and analog/mixed-signal (AMS) content, custom design teams need new ways to address the challenge of quickly and efficiently integrating into existing digital design flows.
Custom Designer leverages the powerful capabilities of Synopsys’ Galaxy™ Implementation Platform to provide a unified solution for custom and digital design teams. Digital teams now have access to a unified, comprehensive AMS block authoring flow with an optimized pipeline that eliminates tedious data exchange and leads to final designs in shorter time.
A Unified Flow with Common Use Model Delivers Fastest Time to Results
Custom Designer LE provides a unified flow based in a common use model, allowing seamless access to Synopsys’ Hercules for LVS/DRC and StarRC for parasitic extraction. Designers simply run Hercules or StarRC as part of the Custom Designer environment to quickly perform physical verification and extraction.
The native integration between Custom Designer SE, Custom Designer LE and StarRC provides a complete round-trip parasitic resimulation flow complete with back-annotation. The comprehensive flow ensures the highest-possible accuracy in parasitics extracted from the physical design.
Figure 2: Custom Designer’s tight integration between schematic, layout and
Custom WaveView speeds design analysis and debug
Advanced P-cells Speed Layout Editing
Custom Designer’s real-time preview of P-cell parameter changes shows the results before committing to placement. Designers instantly see the results of their changes and can quickly adapt the design to significantly speed up the layout editing process.
Custom Designer supports P-cells written in TCL, Python and C++, any of which can be freely mixed in the same design.
P-cell callbacks in Custom Designer LE are also triggered during scripting, helping to eliminate synchronization problems in designs. This capability also supports P-cell abutment when editing or placing cells in batch mode. Scripts can be used for batch-mode processing to create or edit layouts, and abutment will be triggered correctly.
Custom Designer LE also fully supports stretch handles that allow fast on-canvas manipulation of P-cells through graphical means. Users can drag a stretch handle and change the layout of a P-cell quickly, in context with the surrounding objects.
Interoperable PDK Libraries
Interoperable PDK Libraries from the IPL Alliance, an industry-wide collaborative effort to create and promote interoperable process design kit (iPDK) standards, can also be used with Custom Designer. IPL standards enable a single PDK to be used by any OpenAccess tool, thus reducing PDK development and support costs, lowering integration costs and, for the first time, allowing choices in tool selection when building analog/ custom IC design flows.
Figure 3: Bus routing with automatic via up/down and via templates
Time-Saving Automation in Layout
The Automatic Guardring Generator gives the user the ability to create conforming and rectilinear guardrings in real-time. These guardrings are also known as Multi-Part Paths (MPPs). They can be quickly generated with a userspecified separation around a selected set of layout objects. The guardrings are connectivity aware and can be further manipulated via the “Stretch” “Reshape” and “Chop” commands.
Custom Designer’s connectivity driven automatic via insertion feature places DRC-correct vias or via arrays between layers whose net names match. This feature runs in real-time to quickly and accurately complete the layout wiring. The use model works in a simple point and click mode for inserting vias one at a time, or by a window region where vias are inserted in all applicable areas. The function also works down through the layout hierarchy.
An Auto Connect feature allows highaltitude wiring hookups that snap to pins, source, drain and gate connections, reducing the need to zoom in/out to ensure a correct connection that is on grid. Using this feature, designers achieve higher productivity through fewer mouse clicks.
A high-performance interactive bus routing feature allows users to digitize multiple bus bits simultaneously. The bus router automates via up and down functions using a variety of via pattern choices. (See Figure 3.)
Align Assist displays interactive alignment markers that help guide the user to correct alignment, allowing more work to be performed at the high altitude. This function works with all objects on the drawing canvas.
Custom Designer’s Bridge and Tunnel command allows the designer to use a window or a digitized rectilinear shape to specify the locations to rapidly form a bridge (via up) or a tunnel (via down), allowing routes to pass under a given bus or net. Designers are no longer required to manually chop the wires and manually insert vias. This reduces the potential of creating costly DRC violations and avoids the tedious time it takes to correct them. (See Figure 4.)
Shadow mode is a unique highlight mechanism allowing the user to highlight nets in their true respective colors, while dimming the background. The Shadow Mode function also has a dimmer control to set the brightness of the shadowed background. (See Figure 5)
Figure 4: The Tunnel and Bridge command used to clear a routing path
underneath a bus showing the bus before (left) and the bridge after
SmartDRD: Innovative Design- Rule-Driven Technology
Custom Designer LE employs new advanced capabilities to assist with DRC correct editing. This technology is commonly known as Design Rule Driven (DRD) editing. SmartDRD addresses—in real-time—DRC for both mainstream and advanced semiconductor processes with 3 high-performance features:
DRDVisual concurrently checks hundreds of rules, including tablebased, and provides visual feedback in real time (See Figure 6).
DRDAssist enables layout designers to perform DRC correct layout tasks at zoomed-out “high altitude”, greatly reducing the number of zooming-in and zooming-out iterations. DRDAssist will ensure DRC correctness by keeping objects separated at the minimum design rule distance, in-real time. DRDAssist “push through” technology provides a flexible use model by allowing the layout designer to override a design rule violation at anytime just by pushing the cursor through the violation when desired. The repelling function is temporally disabled and then re-enabled to check for the next violation as the designer continues to work. The layout designer is in complete control and the sensitivity threshold for “push through” is user controllable.
DRDAutoFix (Figure 7) employs automatic DRC violation detection and correction that will help greatly reduce the tasks of manually repairing DRC violations which can take more than 40% of the overall layout design cycle time. This new technology provides a powerful productivity boost in custom layout. It uses minimum perturbation algorithms to repair DRC violations as one would do by hand and employs a simple point and- click use model.
Figure 5: Shadow mode enabled for selected net
Figure 6: Design Rule Driven layout with DRDVisual
Open, Interoperable and Extensible Environment
Based on Si2’s OpenAccess database and extensible through the industrystandard TcL scripting language, Custom Designer’s open environment allows CAD groups to quickly add new tools to the environment.
Custom Designer’s open infrastructure is a shift in the EDA industry, offering unfettered access to your design data. With no proprietary languages, databases or extensions, Custom Designer offers CAD groups deep visibility into the system’s design infrastructure, enabling highperformance application integration and development, including access to in-memory data and runtime objects.
Custom Designer’s open infrastructure also provides the ability to develop consistent user interfaces across the Custom Designer environment by providing access to standard components like menus and tool bar icons.
Custom Designer’s open environment also includes a Programmable Netlister that ships with open-source code, allowing quick implementation of custom netlist formats including extracted views. The netlister supports CDF parameters, including PEL/AEL expressions, CDF “simInfo” and netlisting.
Figure 7: Custom Designer’s DRDAutoFix layout productivity feature showing
spacing violations before (left) and after correction
Powerful Capabilities Shared Across Custom Designer Environment
Powerful new GUI technologies provide the entire Custom Designer system with a unique set of capabilities that are shared across all components.
Custom Designer’s property editor allows for single or mass editing of property values across selected instances. Tabbed views simplify editing of different device types and “As-Is” technology clearly indicates mismatches in values.
Custom Designer’s “Transaction History” is a sophisticated undo/redo system that records all data creation and manipulation commands during an editing session for schematics and layout. Recallable at any time, this history is also unique to each different cell view, improving the designer’s recall of the editing steps.
All Custom Designer commands are logged in a log file (.log and .tcl) and can be replayed in the tool. This can be beneficial when creating macros for any task that needs to be repeated.
Icons for recently used commands appear on the history toolbar. Reinvoking previously used commands is easy. Custom Designer also supports standard and user-definable bind-key sets, allowing you to customize the system to meet your unique design style.
Custom Designer boasts a single job monitor that logs all batch and interactive jobs launched from any native Custom Designer tool or any other tool integrated into the environment. Job status is saved across different sessions. Additionally, the Job Monitor can manage jobs submitted to both Sun Microsystems’ Sun Grid Engine and Platform Computing’s LSF loadbalancing products.
- X86 for 32- and 64-bit
- Red Hat Enterprise Linux version 4 and 5 (AS, ES, WS)
- SUSE Linux 10 and 11 (AS, ES, WS)