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Early Optimization of Multicore SoC Architectures Using Synopsys' Platform Architect and Arteris FlexNoC
Learn how to efficiently explore and optimize the dynamic system performance of an Arteris FlexNoC based SoC design in SystemC using a mobile device case study example in Synopsys' Platform Architect.
Kurt Shuler, Vice President of Marketing, Arteris; Patrick Sheridan, Senior Staff Product Marketing, Synopsys; Tim Kogel, Solution Architect, Synopsys
May 15, 2012 | | | SoC FPGA Virtual Target: A Virtual Prototyping Application
In this webinar, you will be introduced to the Altera SoC FPGA for the Altera Cyclone V and Arria V SoC FPGA devices and its associated Virtual Target.
Stephen Lim, Product Marketing Manager, Altera; Marc Serughetti, Product Marketing Director, Synopsys
Apr 19, 2012 | | | LTE-A Physical Layer Design & Simulation
Learn about the LTE-Advanced standard (3GPP Rel.10), its main enhancements over LTE Rel.8 and their impact on the overall system performance.
Dr. Vafa Ghazi-Moghadam, Staff R&D Engineer, Synopsys Inc.
Mar 08, 2012 | | | Programmable Hardware Accelerators Made Easy: Implementing Custom Processors without Compromising Performance, Power or Area
Learn how custom processors or ASIP can provide the right trade-off between flexibility and power, performance and area requirements.
Drew Taussig, Corporate Applications Engineer, Synopsys
Feb 28, 2012 | | | Lowering Validation Costs for Multi-Channel, Wideband Digital Systems Using FPGA-Based Prototyping
See examples of how FPGA-based prototyping can be used to deal with the high data rates of multi-channel, wideband digital systems while reducing systems validation and hw/sw integration costs.
Neil Songcuan, Product Marketing Manager, Synopsys;
Gary Goncher, Applications Engineer and System Architect, Tektronix
Jan 11, 2012 | | | LTE-A Physical Layer Design: Downlink
Learn about the LTE-A standard (Rel.10) with a focus on the downlink configuration, and understand the main enhancements over LTE Rel.8 and their implication on the overall system complexity.
Vafa Ghazi-Moghadam, R&D Engineer, Synopsys
Nov 15, 2011 | | | Using High-Level Synthesis to Streamline ASIC Multi-Rate Communications Design
Learn how high-level synthesis can be used to efficiently create multi-rate hardware for ASIC and FPGA while keeping algorithm development simple.
Chris Eddington, Product Marketing, High-Level Synthesis, Synopsys
Nov 03, 2011 | | | Using High-Level Synthesis and Open Source Imaging Libraries to Streamline ASIC/FPGA IP Development
Introduces a HLS flow from OpenCV (Open Computer Vision) environment using Synphony C Compiler. It will cover techniques in using C++ classes and templates to make re-usable imaging libraries.
Chris Eddington, Product Marketing Manager, Synopsys, Inc.
Oct 13, 2011 | | | Advanced Fault-Injection Methods for Automotive Safety Critical Systems
Learn about fault-tolerance mechanism and fault-injection techniques and HW fault-tolerance mechanisms available in "state-of-the-art" Micro-Controller Units.
Victor Reyes, Technical Marketing Manager, Synopsys; Manfred Thanner, Technical Staff Systems Engineer, Freescale Semiconductor
Sep 29, 2011 | | | Divide and Conquer: Faster FPGA Delivery using Hierarchical, Parallel Design Development
Lean how to use "divide and conquer" hierarchical approaches for parallel machine execution or team-based design, and how to develop, tweak and debug your FPGA design efficiently.
ngela Sutton, Staff Product Marketing Manager, FPGA Implementation, Synopsys
Sep 20, 2011 | | | How to Enable Prototyping of Multi-Million ASIC Gate Designs
Learn how the new HAPS-600 series of FPGA-based prototyping systems enables early hardware & software validation, debug and development for much larger SoC projects than ever before. The webinar introduces this addition to the HAPS family and provides an overview of the complete solution. Designers can reduce initial turnaround times and subsequent iterations with the HAPS-600 series' highly automated software flow from RTL code to the FPGA-based prototype utilizing Synopsys' patented programmable switch routing technology.
Mick Posner, Product Manager FPGA-based prototyping Solutions, Synopsys
Jul 21, 2011 | | | Faster, Safer Implementation of High-Reliability, High Availability Designs using FPGAs
Learn techniques on how to build high operation reliability into your FPGA designs in the face of radiation-induced errors in the field, and how to validate and trace the result of your design implementation before you deploy your FPGA-based system.
Angela Sutton, Staff Product Marketing Manager, FPGA Implementation
Jul 14, 2011 | | | Bringing Up and Optimizing Software Power Management Using Virtual Prototyping
This webinar introduces a solution to the challenges that software developers face when bringing up or optimizing system power management.
Achim Nohl, Solution Architect, Synopsys
Jun 30, 2011 | | | FPGAs in the Signal Path: Comm and Video Apps
Whether it's communications or video, FPGAs are showing up more and more in the signal path because they offer performance to handle the load and flexibility to address a wide variety of signal processing tasks.
IP and libraries, development kits, and board/system level solutions available today for innovative communications and video applications based on FPGAs let designers focus on getting the job done fast.
John Crockett, Applications Engineer, Annapolis Micro Systems;
Rodger Hosking, Vice President & Co-founder, Pentek;
Chris Eddington, Director of Marketing, Synopsys
Jun 23, 2011 | | | Using High-Level Synthesis for the Design and Optimization of Multi-Rate Communications Hardware
In this webinar see concrete examples of how high-level synthesis can be used to efficiently create multi-rate hardware for ASIC and FPGA while keeping algorithm development simple.
Chris Eddington, Technical Marketing Manager, Synopsys
May 25, 2011 | | | Closing the Verification Gap: Integrating Algorithm and RTL Verification for Signal-Processing Apps
Learn how to take advantage of behavioral models for RTL verification to create an integrated signal-processing verification flow from algorithm concept to RTL.
Dr. Holger Keding, Corporate Application Engineer, Synopsys
May 05, 2011 | | | Performance Analysis of ARM CoreLink NIC-301 based Systems Using Synopsys Platform Architect
Hosted by ARM and Synopsys, this webinar highlights system-level methods for performance analysis and optimization featuring Platform Architect, the SBL-301 SystemC Bus Library, and ARM AMBA Designer.
Neil Parris, Interconnect Product Manager, ARM; Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys
Apr 05, 2011 | | | Custom Processors: The Optimal Tradeoff Between Flexibility, Power and Performance
Learn how to easily create efficient custom processors or programmable accelerators using Processor Designer as an alternative to complex, inflexible and difficult to verify fixed hardware blocks.
Drew Taussig, Corporate Applications Engineer, Synopsys
Mar 22, 2011 | | | Advanced Capabilities and Design Interaction with FPGA-Based Prototyping
In order to boost the utility of an FPGA-based prototyping platform, certain critical components are required, including a high-performance, low latency communication channel and direct access to all pins, signals, nodes and registers within the FPGA. Discover how the advanced capabilities of Synopsys HAPS(R) High-performance ASIC Prototyping System(TM) and the new Universal Multi-Resource Bus interface (UMRBus) improves the overall design, verification and software development of an ASIC or SoC.
Mick Posner, Product Manager FPGA-Based Prototyping Solutions, Synopsys
Feb 24, 2011 | | | Scaling High-Level Synthesis for Complex Image and Video Processing Designs
In this one-hour webinar, you will learn about Synphony's basic, high-level synthesis flow for hardware design and verification, how to efficiently synthesize more complex loops and functions in hierarchical C/C++ code, and how to use high-level synthesis for more productive video and image processing in FPGAs and ASICs.
Chris Eddington, Product Marketing Director, High-Level Synthesis
Feb 02, 2011 | | | Team Design for Large FPGA Projects
Team design for FPGAs can be a confusing process if you don't have the right tools and infrastructure in place. Join Amelia Dalton from TechFocus Media as she chats with Jeff Garrison, Director FPGA Implementation Marketing about the unique challenges facing design teams as they take advantage of the incredible power of today's huge FPGAs.
Jeff Garrison, Synopsys
Jan 20, 2011 | | | Performance Validation of Advanced LTE MIMO Receivers Implemented with Xilinx LogiCORE IP
Learn how Xilinx MIMO IP can help you implement advanced MIMO receivers for LTE base stations (eNodeB) with up to 4 Multi-User MIMO codewords and validate its performance in the Synopsys LTE library.
Dr. Bo Wu, Technical Marketing Manager for System-level Solutions, Synopsys; Mark Quartermain, Sr. Product Marketing, Xilinx, Inc.
Jan 12, 2011 | | | LTE Physical Layer Design: Basics
Overview of the LTE standard, LTE simulation library and Synopsys SPW algorithm design tool.
Bo Wu, Technical Marketing Manager, Synopsys
Sep 15, 2010 | | | LTE Physical Layer Design: Optimization
Learn more about LTE physical layer design and how design choices can impact implementation and performance.
John Lundell, R&D Manager, Synopsys
Aug 18, 2010 | | | Simulation in Photovoltaics with TCAD Sentaurus and Saber
This webinar focuses on optimization of rear point contact solar cells using 3-D TCAD simulation and addresses system-level simulation of PV arrays
Joanne Huang, TCAD R&D Engineer & Kurt Mueller, Saber Business Development Manager, Synopsys
Jul 22, 2010 | | | LTE Physical Layer Design: Synchronization
Learn more about some of the features of the LTE User Equipment (UE) acquisition and synchronization process.
Louie Valena, Corporate Applications Engineer, Synopsys
Jul 21, 2010 | | | Complementing Emulation with FPGA-Based Prototyping
Discover how FPGA-based prototyping is used as a natural progression to complement emulation when the shortening of development time is critical to the overall success of ASIC and SoC projects.
Neil Songcuan, Synopsys
Mar 31, 2010 | | | The Big Design Squeeze: How to get faster design turns in FPGA-based designs
Whether you are using FPGAs to verify your ASIC or as a final implementation platform, this webinar will illustrate techniques to help you speed up your synthesis iterations by a factor of 2 vs. traditional approaches, and achieve up to 2 times the turnaround time from RTL to board with better results stability from one run to the next. Techniques for more efficient debug and optional team design techniques are also covered.
Angela Sutton, Synopsys
Mar 03, 2010 | | | Low Power Algorithm Exploration
Learn how to use the Synphony high-level synthesis tool to do architectural power exploration within days of a having a high level algorithm model in MATLAB or Simulink.
Chris Eddington, Director of Product Marketing, Synopsys; Josefina Hobbs, Technical Solutions Architect, Synopsys
Jan 19, 2010 | | | Achieving predictable success in FPGA Projects
This 3-part series introduces Synopsys tools for FPGA users, including model-based algorithmic design, IP integration tools, tightly coupled constraint and analysis environments, integrated synthesis and placement, and on-board assertion-based verification linked to RTL simulation.
Doug Amos and Paul Schoukroun, Synopsys
Mar 09, 2009 | | | Using Simulation to Implement a Robust Design Flow
Listen to our Robust Design Web Seminar to discover how Robust Design methodologies coupled with Synopsys' Saber simulation and analysis solution can improve your design performance and reliability for mechatronic systems.
Mike Jensen, Corporate Applications Engineer, Synopsys
Dec 10, 2006 | | |
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