VDK Family Delivers Fast Software Bring-Up and Better Debug Control for Quad-Core ARM® Cortex™-A15 MPCore™ Processor and ARM big.LITTLE™ Processing-Based Designs

Collaboration Delivers Realistic Multicore System Simulation Using Transaction-Level Models of FlexNoC Interconnect with Platform Architect

Processor Designer Doubles Functionality for XMP-1 Sound Generator Device while Reducing Development Cost

Synopsys announced the use of its comprehensive and proven Virtual Prototyping Solution in Altera Corporation's (Nasdaq: ALTR) newly announced SoC FPGA Virtual Target software development platform. The Virtual Target enables engineers to begin writing software for systems based on Altera's SoC FPGAs months before hardware availability, reducing development time and costs. Altera chose to leverage Synopsys' Virtual Prototyping Solution due to its comprehensive and proven technology, highly productive debugging and analysis tools for multicore platforms and broad model portfolio, which includes transaction-level models of the ARM® Cortex™-A9 processor and Synopsys DesignWare® IP.

Altera announced availability of the FPGA industry's first virtual target designed to enable immediate device-specific embedded software development targeting Altera's newly announced SoC FPGA devices.

Synopsys announced the launch of TLMCentral (link TLMCentral to www.tlmcentral.com, if possible) the first industry-wide web portal for developers and users of transaction-level model (TLM) technology. TLMCentral aggregates information about free and commercial system-level models of common system-on-chip (SoC) components from leading semiconductor IP vendors, tool providers, service companies and universities. TLMCentral is an open portal that will ease and accelerate the development of virtual prototypes across the industry. It is available at no cost to users and providers of transaction-level models.

Synopsys and ARM® announced a licensing agreement enabling Synopsys to distribute ARM's Fast Models and create models of ARM Cortex Series processors.

Virtualizer Accelerates Software Development Schedules By Up To Nine Months with Lower Engineering Effort

Integrated Design and Measurement Technology Bridges LTE/LTE-Advanced Algorithm Design and System Integration

Using Processor Designer, Yokogawa saved significant development and verification time by automatically generating software development tools. As part of Synopsys' System-Level Design portfolio, Processor Designer automates the design of custom processors giving IP block designers an easy-to-use, high performance alternative to creating fixed processing hardware or application-specific processors in-house.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and Xilinx, Inc. (Nasdaq: XLNX), the industry leader in programmable logic, today announced the availability of the FPGA-Based Prototyping Methodology Manual (FPMM), a practical guide to using FPGAs as a platform for system-on-chip (SoC) development.

HAPS-600 Series Offers High Flexibility and Scalability for Larger FPGA-Based Prototyping Projects with up to 81 Million ASIC Gates

Synopsys announced the broad availability of Platform Architect with Multicore Optimization Technology, a new solution for performance analysis and early definition of multicore system architectures in SystemC. Using Platform Architect with Multicore Optimization Technology, designers of SoCs, chipsets and systems can capture hardware/software performance models of multicore system architectures in the early concept phase for robust performance measurement and trade-off analysis, months prior to software availability.

Synopsys announced that Mazda Motor Corporation, a leading producer of automobiles, has adopted Synopsys CoMET-METeor virtual prototyping solution to verify their Electronic Control Units (ECUs). Over the last year, Mazda has been using the METeor embedded software development environment to conduct its ECU system verification in a virtual environment. By decreasing the number of tests on real automobiles and hardware-in-the-loop (HILS) test equipment, the virtual prototyping solution will enable Mazda to save significant time and cost.

Synopsys announced the availability of the Time Division Duplex (TDD) mode in its Long-term Evolution (LTE) Model Library for physical layer system simulation.

Synopsys announced it has acquired technology, engineering resources and other assets of Synfora, Inc., a provider of C/C++ high-level synthesis tools used to design complex systems-on-chips (SoCs) and FPGAs.

Next-generation systems deliver highest performance, highest capacity, pre-tested IP and unique advanced verification functionality

Synopsys has completed the acquisition of CoWare, Inc., a global supplier of software and services for electronic systems design. The acquisition will expand Synopsys' portfolio of system-level design and verification products used in wireless, consumer and automotive design.

Enhances Model Authoring Efficiency and Simulation Performance Utilizing Multicore Capabilities

Synopsys announced it has acquired VaST Systems Technology Corporation to extend its virtual prototyping solutions into the automotive and consumer application space. The acquisition adds a comprehensive set of processor sub-system models frequently found in automotive and consumer applications to Synopsys' virtual prototyping portfolio.

Synopsys announced the availability of SuperSpeed USB 3.0 transaction-level models (TLM) supporting the Open SystemC™ Initiative (OSCI) TLM-2.0 API specification. The models are TLM representations of the Synopsys DesignWare® SuperSpeed USB 3.0 Device and xHCI Host Controller IP.

New CoWare SBL-301 SystemC Bus Library for CoWare Platform Architect provides configurability, visibility and rapid turn-around time, enabling system designers to efficiently optimize AMBA NIC-301 network interconnect-based designs

Synopsys today announced its System-Level Catalyst Program to accelerate the adoption of system-level design and verification.

JEDA Technologies announced today the availability of its TLM-2.0 Compliance Checker for high-level SystemC models. The product targets high-level OSCI TLM-2.0 model developers and OSCI TLM-2.0 compliant Virtual Platform users. The checker reduces high-level SystemC model development time and ensures interoperability with OSCI TLM-2.0 models coming from various sources.