Low Power System-Level Design    

 

Designing for low power and energy consumption optimization are key issues for chip developers. The earlier low power techniques can be applied to the design, the bigger their effect on overall power consumption. But low power design is not just a hardware issue; software running on the chip has a significant effect on the amount of power it consumes. Design teams also realize that power envelopes have effectively stopped the traditional evolution of processor performance scaling and are switching to multicore design. Virtual prototypes address the need for early, software-driven power analysis and optimization, as well as low-power embedded software development for single and multicore designs.

PDF Low Power Brochure (PDF)

 

 
Platform Architect provides architects and system designers with SystemC TLM tools and methods for the efficient design, performance analysis and optimization of multicore SoC architectures.


 
A comprehensive solution for the creation, assembly, and execution of SystemC-based virtual prototypes for pre-silicon software development and software-driven verification.

By introducing power management earlier in the design flow, at the system-level, design teams can benefits in several areas. From hardware block IP performance to software development, test and integration, designers can take advantage of many techniques to reduce power.

Synopsys offers power management techniques as part of all the tools in our system-level design portfolio. This includes: power conscious block design with algorithm design, high-level synthesis and custom processor design tools; architecture design to optimize power across multicore SoCs; and virtual prototyping which allows designers to characterize and estimate power information for embedded software development and system validation up to 6 months earlier in the design flow.



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