HAPS®-70 Series   

FPGA-Based Prototypes with the Highest Performance and Scalable Capacity 

The HAPS-70 series is an easy-to-use and cost effective FPGA-based prototyping system. The HAPS-70 series enables early hardware/software integration and system-level validation at near-real-time run-rates, using at-speed, real-world interfaces.

Enhancements to the HAPS system technology, as well as the use of the latest Xilinx Virtex®-7 FPGAs, provide designers using the HAPS-70 series with superior capacity, performance, and advanced verification modes. The HAPS-70 series enables SoC designers to build next generation designs faster, with less risk, and more profitably.

HAPS-70 Product

For more information on the HAPS-70 series contact your local Synopsys sales office or send an email to fpga-based-prototyping@synopsys.com.

HAPS-70 Features:
  • Modular system architecture scales from 12-144M ASIC gates to accommodate a range of design sizes, from individual IP blocks to processor sub-systems to complete SoCs. For system capacity ranging from 500k-4M ASIC gates, see the HAPS Developer eXpress Series.
  • Enhanced HapsTrak 3 I/O connector technology with high speed time-domain multiplexing delivers up to 3x performance improvement in data throughput over traditional pin multiplexing
  • System definition and bring-up utilities speed hardware assembly and ensure the prototype’s electro-mechanical integrity
  • Advanced power and cooling management
  • Design planning tools reduces time-to-prototype by 2-3 months streamlining the transition from block level IP validation to full system integration
  • Improve debug efficiency with 100x greater visibility and 8x faster download time of debug trace buffer data
  • Advanced use modes including co-simulation, transaction-based verification, and hybrid prototyping
  • HAPS-70 FPGA-based prototyping systems are available in nine model variants, with capacities from 12 to 144 million ASIC gates
HAPS Hardware Accessories and Software

High Performance
Performance is what has made the HAPS family the industry leader for a range of validation scenarios from independent IP blocks to full systems that integrate CPU subsystems. Hear about Synopsys’ next generation FPGA-based prototyping system, the HAPS-70 Series, from Joachim Kunkel, Senior VP & GM of the Synopsys Solutions Group.

HAPS-70 Intro video

Scalable Capacity
A modular hardware architecture along with the latest high-capacity FPGA technology allows for HAPS-70 series systems to scale from 12M to 144M ASIC gates.

Deep Visibility
Seamless debug visibility across FPGAs and a spectrum of trace storage options allow you to deep access and control with minimal impact to prototyping resources.

HAPS Deep Trace Debug video

Easy Bring-Up
IP and ASIC RTL migration technology from the industry's leading EDA vendor reduces your effort to deliver high-performance prototypes.

Connectivity Options
The benefits of stand-alone FPGA-based prototypes are clear, but co-simulation and transaction-based validation connectivity for HAPS-70 eases migration from an RTL simulation environment and enable a hybrid system that integrates SystemC/TLM models for the fastest SoC prototype bring-up ever.

HAPS-Specific Design Planning Features
Synopsys' Certify ASIC prototyping software is tightly integrated with the Synopsys HAPS Family of FPGA-based prototyping hardware to ease design planning tasks. In addition to the features to ease RTL code conversion and ASIC design partitioning across multiple FPGAs, tight integration of HAPS systems allows Synopsys to offer unique solutions for HAPS:

  • Plan and implement HAPS systems immediately with Certify's extensive library of motherboard and daughter board descriptions
  • Quickly bring-up multi-board HAPS system prototypes with Tcl-based system target scripting
  • Eliminate FPGA I/O congestion by sharing Xilinx Virtex-7 high-speed pin pairs of HAPS-70 systems
  • Obtain highly accurate prototype performance reviews of HAPS-70 systems with multi-chip, system-level static timing analysis

HAPS-Specific Connectivity and Debug Features
Synopsys' Identify RTL debugger and HAPS UMRBus (Universal Multi-Resource Bus) Interface Kit connects HAPS to a host workstation for system monitoring, RTL debug, and advanced verification. In addition to the features to ease RTL debugging of FPGAs, tight integration of HAPS systems allows Synopsys to offer unique solutions for high capacity debug and system connectivity:

  • Quickly assemble and confirm the integrity of multi-motherboard and daughter board systems with HAPS-Aware hardware query and checks for clock validity, HSTDM links, and UMRBus connections
  • Apply a HAPS Deep Trace Debug SRAM daughter board for 100X signal visibility over traditional FPGA logic debuggers
  • Improve prototype state visibility by data streaming between HAPS and a host workstation with HAPS UMRBus interface
  • Apply an external logic analyzer for sophisticated triggering and high-capacity sample storage. Use the Identify Real Time Debug (RTD) option with a HAPS Mictor Daughter Board to instrument RTL then easily program and connect Agilent or Tektronix Logic Analyzer to a HAPS system

Troubleshoot and Debug Made Easier
For additional information on HAPS Deep Trace Debug and other Synopsys tools that can help troubleshoot your FPGA-based prototype and quickly isolate RTL bugs.

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