HAPS Transaction-Based Validation Suite 

Utilities for Additional HAPS System Connectivity 
The HAPS Transaction-Based Validation (TBV) Suite is a comprehensive set of software tools and libraries that enables the connection between a HAPS Series FPGA-based prototype system and a host workstation to enable hybrid prototyping transaction-based verification. These connectivity options allow HAPS FPGA-based prototypes to support a variety of hardware/software validation scenarios with Synopsys Virtualizer™ or VCS®.

Typical Product for Expanded Verification Scenarios with HAPS
Figure 1. Typical Product for Expanded Validation Scenarios with HAPS

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The library resources of the HAPS Transaction-Based Validation Suite are distributed with the products of Table 1.

FeaturesHAPS System SupportProduct Distribution
Synopsys Transactor Library for AMBA InterconnectsHAPS-DX/70
HAPS-DX only
HAPS-70 only
HAPS-60 only
ProtoCompiler
HAPS-DX TBV Suite1.
HAPS-70 Co-Sim & TBV Suite2.
HAPS-60 Co-Sim & TBV Suite2.
Transaction-Based Verification Environment (SCE-MI)HAPS-DX/70
HAPS-DX only
HAPS-70 only
HAPS-60 only
ProtoCompiler
HAPS-DX TBV Suite1.
HAPS-70 Co-Sim & TBV Suite2.
HAPS-60 Co-Sim & TBV Suite2.

Table 1. HAPS TBV Suite Features, HAPS System Support, and Products

1 For use with ProtoCompiler DX
2 For use with Certify

Synopsys Transactor Library for AMBA Interconnects
The Transactor Library for AMBA interconnect is the interface that facilitates the data exchange between a loosely-timed transaction-level model (TLM) and a cycle-accurate FPGA hardware implementation. The transactors give designers the flexibility to partition the SoC design between the SystemC/TLM virtual and FPGA-based prototyping environments at the natural block-level boundaries of the AMBA interconnect. The transactors support a range of AMBA Interconnect, including AHB™/APB™, AXI3™, AXI-4™ and AXI4-Lite™.

Learn more about Synopsys Hybrid Prototyping

Software and Hardware Transactors
Figure 2. Software and Hardware Transactors

The transactor library provides the following key elements:
  • Logic that links a host workstation to FPGA systems
  • Connects abstract SystemC models to live FPGA hardware
  • AMBA protocol interface for SoC block communication

Transaction-Based Verification Environment
The transaction-based verification environment for the HAPS Series provides a SCE-MI standard transport infrastructure to connect untimed software models to design-under-test (DUT) models executing within a hardware system like an FPGA-based prototype. The Synopsys SCE-MI communication link is automatically generated for each channel which interconnects transactor models in a HAPS Series FPGA-based prototype to untimed or RTL C/C++/SystemC models on a workstation.

Key needs addressed by the transaction-based verification environment include:
  • SCE-MI Accellera-compliant connectivity to HAPS Series systems
  • Support for SystemVerilog Import/Export DPI functions
  • Eases connectivity to HDL simulators like Synopsys VCS



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