The HAPS®-60 Co-Simulation (Co-Sim) and Transaction-Based Validation (TBV) Suite is a comprehensive set of software tools and libraries that enables the connection between a HAPS-60 Series FPGA-based prototype system and a host workstation to enable hybrid prototyping
, co-simulation or transaction-based verification. These connectivity options allow HAPS FPGA-based prototypes to support a variety of hardware/software validation scenarios with Synopsys Virtualizer™ or VCS®.
Figure 1. Typical Product for Expanded Verification Scenarios with HAPS
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Synopsys Transactor Library for AMBA Interconnects
The Transactor Library for AMBA interconnect is the interface that facilitates the data exchange between a loosely-timed transaction-level model (TLM) and a cycle-accurate FPGA hardware implementation. The transactors give designers the flexibility to partition the SoC design between the SystemC/TLM virtual and FPGA-based prototyping environments at the natural block-level boundaries of the AMBA interconnect. The transactors support a range of AMBA Interconnect, including AHB™/APB™, AXI3™, AXI-4™ and AXI4-Lite™.
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Figure 2. Software and Hardware Transactors
- The transactor library provides the following key elements:
- Logic that links a host workstation to FPGA systems
- Connects abstract SystemC models to live FPGA hardware
- AMBA protocol interface for SoC block communication
- Co-Simulation Environment
The co-simulation environment establishes a signal-level link between a HAPS-60 series system and Synopsys VCS®. This allows the entire SoC design, or parts of it, to run in the hardware during the simulation phase.
Key needs addressed by the co-simulation environment include:
- An incremental way to move portions of a design into the FPGA-based prototype
- Drive the FPGA-based prototype with an HDL test fixture
- Co-simulation with prototype to ensure equivalent function
Figure 3. HDL-Bridge for Co-Simulation
Transaction-Based Verification Environment
The transaction-based verification environment for the HAPS-60 series provides a SCE-MI standard transport infrastructure to connect untimed software models to design-under-test (DUT) models executing within a hardware system like an FPGA-based prototype. The Synopsys SCE-MI communication link is automatically generated for each channel which interconnects transactor models in a HAPS-60 series FPGA-based prototype to untimed or RTL C/C++/SystemC models on a workstation.
- Key needs addressed by the transaction-based verification environment include:
- SCE-MI Accellera-compliant connectivity to HAPS-60 systems
- Support for SystemVerilog Import/Export DPI functions
- Eases connectivity to HDL simulators like Synopsys VCS