HAPS-600 Series of High Capacity FPGA-Based Prototyping Systems 


HAPS-600 High Performance and Higher Capacity Prototyping
The HAPS-600 series extends Synopsys’ HAPS family of FPGA-based prototyping products with a higher capacity solution that supports designs up to 81 million ASIC gates equivalent. The HAPS-600 series offers the highest flexibility with a scalable architecture that is based on the Xilinx Virtex-6LX760 FPGAs. The solution also includes native support of co-simulation, transaction-based verification and links to virtual prototyping via the UMRBus communication interface – allowing high debug visibility earlier in the design cycle.

PDFHAPS-600 Datasheet

HAPS-600 Benefits
  • Accelerates time-to-market
  • Early software development
  • Lowers total cost of ownership
  • Reduces design & development risk

HAPS-600 Series: High-performance & Higher Capacity Prototyping

HAPS-600 series – prototyping higher capacity designs
  • Completes the HAPS product portfolio
    • Fills the gap for high capacity ASIC prototyping
    • Handles up to 81 M ASIC gates
    • Compatible with HapsTrak II daughter boards
  • Highest flexibility for high capacity prototyping
    • Scalable system architecture with 6, 9, 12, 15 or 18 Virtex-6 LX760 FPGAs
    • Highest FPGA and daughter board interconnection flexibility through patented switching technology
  • Automated design implementation, various debug capabilities and support of advanced use modes
    • Tight integration with HAPS-600/CHIPit Manager design implementation and system configuration software for an easy, quick and guided design implementation
    • Seamless, integrated debug center and Identify debug tool offers extensive debugging capabilities on different levels
    • Support of co-simulation, transaction-based acceleration and connection to Virtual Prototyping over a UMRBus communication interface

Hardware/Software Co-development
By incorporating real world interfaces operating at near real world speeds the HAPS-600 series enables effective hardware/software co-development, debug and validation. User selected, unit level pre-instrumentation ensures debug visibility at design points of interest while maintaining high system performance.

Support by a comprehensive, automated and easy-to-use design implementation flow utilizing Synopsys’ Synplify FPGA synthesis tool ensures a streamlined and high quality of results (QoR) flow from ASIC RTL to hardware.

Automated FPGA-Based Prototyping
HAPS-600 series of automated FPGA-based prototyping systems provide functional verification and validation for the entire SoC and ASIC design process. Throughout the verification process HAPS-600 series gives design engineers superior speed and flexibility for hardware verification, pre-silicon software development, and system validation. The multifunctional system can be used in multiple verification modes, including cycle/event-based co-simulation, SCE-MI compliant transaction-based verification and in-circuit prototyping to significantly reduce the overall design and verification time. The patented programmable interconnect architecture in combination with a comprehensive software suite enables more automation and the highest productivity for design implementation, verification and debug.

HAPS Daughter Boards and Accessories

For information on the previous generation of Automated FPGA-Based Prototyping systems using Virtex-5 FPGAs visit http://www.synopsys.com/Systems/FPGABasedPrototyping/CHIPit/Pages/default.aspx

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