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Interconnect System Components
HAPS to HAPS accessories
External Clock Distribution Board
The HAPS® External Clock Distribution Board (ECDB) extends direct synchronization of clocks to connect or interface up to six HAPS systems together. The HAPS ECDB automatically replicates input clocks to the output clocks to support up to twelve clocks across six HAPS-60 or HAPS-70 systems capable of supporting up to 288M ASIC gates.
The BIO1 contains LED indicators, push buttons and a USB port to support direct access to the design for debug purposes. The card is controlled via a GPIO header on a HAPS motherboard. Several BIO1 cards can be stacked together side-by-side to expand the number of I/O functions.
TERM-TOP_1x1 Termination Daughter Board
The TERM-TOP_1x1 is a termination board especially designed for terminating global buses between several motherboards in the HAPS-50 series. Termination boards are recommended on the first and last connector in the chain. Two of these boards are already included in HAPS-54 deliveries.
LAB_1x1A Daughter Board
The LAB_1x1A is perfect for small hand-built experiment designs, and also provides easy access to measure points for all signals in a HapsTrak II connector. The signals from the HapsTrak II connector are evenly spread out in two areas, one with a 2 mm grid and the other with a 0.1" grid.
STB2_1x1 Test Board
The STB2_1x1 is a board for testing purposes, used in combination with the self-tests for motherboards in the HAPS-50 series. With STB2_1x1, it is possible to detect open circuits as well as power and ground faults in any HapsTrak II connector.
Interface HAPS to other systems
The MICT_1x1 board makes all signals in one HAPS connector available in four 38-pin Mictor connectors for easy access with a logic analyzer. It can be placed directly on the HAPS motherboard or stacked on a daughter board.
Interfaces supporting standard protocols
LAI_HT3 Daughter Board
The HAPS® Logic Analyzer Interface (LAI_HT3) board allows probing of dedicated signals with standard Logic Analyzers. The LAI_HT3 is a pass-through board for all power and I/O signals passing through a single HapsTrak 3 connector on a HAPS system.
The USB3_HTII is a HAPS daughter board providing a single port USB 3.0 physical layer interface. The daughter board supports USB 3.0 Device operation when utilized alongside the DesignWare USB 3.0 digital controller IP (sold separately) or other 3rd party controller IP.
High Speed I/O Virtex-6LXT Daughter Board
The High Speed IO Virtex-6LXT daughter board allows high speed interface standards such as PCIe Gen 2, SATA 6 Gbps, and Gigabit Ethernet to interface with the HAPS-60 or HAPS-50 systems. The High-Speed I/O board can be connected to the HAPS-60 series or HAPS-50 series systems as a daughter board through two standard HapsTrak II connectors. The High Speed IO board features the Xilinx Virtex-6 XC6VLX75T FPGA which includes 12 GTX transceivers to enable the support for high speed interfaces.
The PCIE-1-KIT board is a one-lane PCI Express solution for HAPS, including: PCIE 1_1x1: 1-lane HAPS daughter board, PCIE-4_PC: 4-lane host interface board, and PCIE-4_CABLE: 4-lane cable, 1 meter in length.
The DDR3_HS_1x2 HAPS daughter board contains nine DDR3 devices with a memory organization of 9 x 512M x 8bit that allows chip developers to interface ASIC/SoC designs with an external high capacity and high performance DDR3 memory module using HapsTrak II connectors. The DDR3 daughter board is targeted to run at a clock rate of 400MHz.
FLASH_1x1_HTII Daughter Board
The FLASH_1x1_HTII HAPS daughter board contains two 1Gbit NOR Flash PROMs, accessible as 8-bit or 16-bit wide words.
DDR3_1x2 Daughter Board
The DDR3_1x2 board is an interface between HapsTrak II and a 240-pin UDIMM (Unbuffered Dual Inline Memory Module) DDR3 SDRAM module.
DDR2_1x2_SODIMM_HTII Daughter Board
The DDR2_1x2_SODIMM_HTII daughter board is a 200-pin SODIMM DDR2_SDRAM module that allows chip developers to interface ASIC/SOC designs with an external high capacity and high performance DDR2 memory module using HapsTrak II connectors used with the HAPS-60 series.
The SRAM_1x1_HTII board contains a synchronous SRAM subsystem. The memory is organized in 2Mx72bits. The default operation mode is Pipeline.