|High Throughput GSPS Signal Processing Using Synthesizable IP Cores|
This whitepaper illustrates how parallel processing synthesizable IP cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or reduce power with sub-linear increases in area.
Sunil Ashtaputre, Director of R&D, Synopsys; Baijayanta Ray, DSP IP Architect, Synopsys
|Integrating High-Level Synthesis Designs into SoCs with Less Effort and Risk|
High-Level Synthesis (HLS) has many benefits for integrated circuit design but also introduces challenges for integration into SoCs. This paper proposes solutions that improve HLS system integration by eliminating manual interface specification, reducing debug and allow system integration and verification tasks to be performed earlier. By enabling an HLS to SoC flow from a model-based design environment, these methods increase productivity and eliminate manual effort, errors and risk.
Chris Eddington, Sr.Technical Marketing Manager for High-Level Synthesis, Synopsys
|Efficient Design and Verification of Digital Communication Systems|
LTE and WiMAX are key contenders for next generation mobile phone system. Both standards are excellent examples to highlight the huge complexity involved in modern communication algorithms. This increasing complexity is the trigger for new design methodologies and tools. This white paper provides a detailed analysis on the elements that determine algorithm design and verification efficiency for LTE and WiMAX communications systems. The concept of efficiency is discussed for modeling, simulation, reuse, and verification. Different methodologies and simulation solutions are then compared, providing the reader with specific algorithm design requirements.
Markus Willems, Ph.D., Product Marketing Manager, Synopsys and Holger Keding, Ph.D., Corporate Application Engineer, Synopsys
|No Room for Error: Creating Highly Reliable, High-Availability FPGA Designs|
Designers of FPGAs for military and aerospace applications need to increase the reliability and availability of their designs. This is particularly true in the case of mission-critical and safety-critical electronic systems. This paper provides brief definitions of key concepts: mission-critical, safety-critical, high-reliability and high-availability. It then considers the various elements associated with the creation of high-reliability and high-availability FPGA designs including: FPGA design and verification flows, methodologies, processes and standards, architectural and algorithmic exploration, geographically distributed design teams, IP selection and verification, DO-254 compliance and much more.
Angela Sutton, Staff Product Marketing Manager, Synopsys