Processor Designer eUpdate, September 2013 

 

Welcome to the second issue of the Processor Designer eUpdate Newsletter, our bi-annual publication to keep you informed on topics related to Processor Designer™: latest tool enhancements, upcoming events, success stories, plus application domains that deploy application-specific processors.

To date, more than 100 million devices have featured application-specific instruction-set processors (ASIP) designed with Processor Designer. Processor Designer customers are involved in a wide range of application domains, deploying ASIPs for a specific reason; to meet power, performance and area goals while achieving programmability.


What’s New in Processor Designer?
Since our last eUpdate in March 2013, Processor Designer has had releases in June and September, following our quarterly release schedule. So, it is always a good idea to review the latest release notes.

Below are highlights released during the past 6 months:
  • LLVM Compiler Backend Generation – Processor Designer now generates an architecture-specific compiler backend using the open-source LLVM compiler framework. LISA has been extended to capture all compiler-specific information; with optional GUI support for assistance authoring compiler-specific LISA sections.
  • Full 64-bit support - Processor Designer now fully supports 64-bit generation architectures (both address and program counters), driven by the demand to build ASIPs for big-data applications. Full 64-bit support includes compiler, assembler, linker and debugging capabilities.
  • Support for AXI and Streaming Protocols – The protocol library has been further extended to support the standard AXI Master interface as well as handshake-based streaming protocols. As with all other protocols in the library, the new interfaces can be instantiated seamlessly into any processor design.
  • Eclipse for Source Level Debugging - Processor Designer now ships a customized version of Eclipse, which supports convenient source level application debugging. The customized Eclipse debugger can connect to several local and remote simulations and hardware. In addition, Eclipse's memory viewer is enhanced to support multiple memory spaces, which can be conveniently added to the generated software development kit.
  • Enhanced For-Loop Support - Processor Generator now supports unrolling of "for"-loops in the behavior section. Specifically, it now allows the user to access resource arrays within the loop body.
  • Registers Without Reset - Processor Generator now allows the option to remove the reset input from selected registers, which can result in significant area savings in the generated hardware due to smaller flip-flops.

For a Processor Designer update, please contact your local Synopsys office or contact us here.


Application Domain: Embedded Vision
In the March 2013 eUpdate, we introduced Embedded Vision as a domain showing the key characteristics that motivate application-specific processors: where huge amounts of data demand high performance, the implementation as an embedded device requires energy efficiency and the evolution of algorithms calls for programmability. Processor Designer is a natural selection and is being widely deployed in this application domain.

In April 2013, Synopsys announced the availability of the Embedded Vision Development System. It enables our customers to jump-start the design of an Embedded Vision ASIP. The Embedded Vision Development System features a small RISC core with a C/C++ compiler, all provided in fully modifiable source code. It also includes a ported OpenCV library, examples on how to build programmable accelerators, the RTL design flow and the HAPS FPGA-based prototyping flow. Below are links to learn more about the Embedded Vision Development System, featuring the news release and video of the product, case studies and a white paper touching on the design methodology.


Success Stories
In July, we published our latest success story featuring Fujitsu Laboratories. The story covers the deployment of Processor Designer to design a DSP for a 3G/LTE multimode modem. Modem design is another ASIP hotspot, with many Processor Designer users designing custom processors for this domain. We will cover modem design as another application domain in an upcoming eUpdate. Read below why Fujitsu Laboratories selected Processor Designer to build an ASIP:
Processor Designer customers are involved in a wide range of application domains, as reflected by these additional success stories:

Upcoming Events
Meet the Processor Designer application experts at the following events:

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