Processor Designer eUpdate, March 2013 


Welcome to the first issue of the Processor Designer eUpdate Newsletter. To date, more than 100 million devices have been featuring application specific processors (ASIP) designed with Processor Designer. Processor Designer customers are involved in a wide range of application domains, deploying ASIPs for a specific reason; to meet power, performance and area goals while achieving programmability.

This newsletter serves multiple purposes:

What’s New in Processor Designer?
Processor Designer follows a quarterly release schedule, with releases in March, June, September and December. These regular releases ensure new features, enhancements and bug fixes are distributed as soon as they are implemented. So, it is always a good idea to review the latest release notes.

A few highlights that were released in the past 6 months:
  • Enhanced debugger integration – Automated source level debugging instrumentation for Dwarf2 format
  • Custom HDL insertion capability – Processor Designer now supports a convenient way of integrating external HDL blocks with the LISA model. An HDL block can be placed both inside a UNIT, as well as at the boundary of the design
  • Compiler Designer enhancements – Enhanced compiler quality, reducing compiler build time, supporting multiple memory spaces, creation of composite registers and more
  • Decoding capability – The ability to decode in multiple pipelines, other than the root pipelines

For a Processor Designer update, please contact your local Synopsys office or contact us here.

Application Domain: Embedded Vision
Embedded vision is about extracting meaning from visual inputs. Or to quote Jeff Bier, founder of the Embedded Vision Alliance, it is about “designing machines that can see”. Embedded vision applications show the key characteristics that call for application specific processors: the huge amount of data calls for high performance, the implementation as an embedded device calls for energy efficiency and the evolution of algorithms calls for programmability. Not as a surprise, Processor Designer is widely deployed in this application domain.

In January 2013, Synopsys ran a webinar titled “Implementing Embedded Vision Applications Optimized for Power, Performance and Programmability” (the recording is available online) highlighting why ASIPs are ideally suited for Embedded Vision applications.

The webinar also introduces the Vision Processor Starter Kit, which gives a head-start for the design of an Embedded Vision ASIP. The Starter Kit features a small RISC core with a C/C++ compiler, a ported OpenCV library, examples on how to build programmable accelerators, the RTL design flow and the FPGA-based rapid prototyping flow. Using the example of Canny Edge Detection (which is also included in the starter kit), the webinar demonstrates how the Vision Processor Starter Kit can be used to design an optimized programmable architecture. The Vision Processor Starter Kit is available immediately. Please contact your local Synopsys office or contact us here.

Success Stories
Processor Designer customers are involved in a wide range of application domains, as also reflected by these success stories:

Upcoming Events
Meet the Processor Designer application experts at the following events:

Interested in regular updates on Processor Designer news and products? Sign up for our bi-annual newsletter!

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