High-Level Block Design  

Accelerate Innovation by Getting to the Right Design Faster  

Rapidly explore, specify and simulate differentiated IP blocks for your SoC design. Achieve the fastest simulation of signal processing algorithms using SPW or System Studio and associated DSP model libraries supporting the latest standards such as LTE. With Synphony High-Level Synthesis, quickly create synthesizable RTL from high-level C/C++ or model-based designs to eliminate months of implementation and verification effort.

 

System Studio
Model-based design creation, simulation and analysis of complex, digital signal processing (DSP) algorithms.
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System Studio Libraries
More than 3000 ready to use models, supporting the analysis and design of protocols and standards in the wireless and digital signal processing domain


SPW
The path from innovation to implementation for digital signal processing design including C data flow (CDF) support
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SPW Model Libraries
Model libraries to accelerate the design of communication systems, featuring the latest standards, including the LTE model library.

  • DSP Design
  • High-level synthesis and accelerated verification for signal processing  

Synphony Model Compiler
Faster, more efficient ASIC & FPGA HW Development for DSP Algorithms

  • High-Level Synthesis
  • High-Level Synthesis from Language and Model-based Design 

Synphony C Compiler
High-level synthesis to accelerate design of image processing IP

System Studio Libraries
More than 3000 ready-to-use models supporting the analysis and design of protocols and standards in the wireless and digital signal processing domains

SPW Model Libraries
Model libraries to accelerate the signal processing design of communication systems, featuring the latest standards, such as the LTE model library

Differentiated SoC Block Design with Higher Productivity and Speed
  • Broadest portfolio of tools for SoC IP block creation at the electronic system level, including signal processing algorithm design, high-level synthesis, and application-specific processor design
  • Multiple paths from higher levels of abstraction to implementation, verification and prototyping
  • Both language- and model-based design tools with an extensive selection of models to raise productivity and shorten schedules
  • Proven reference designs, templates, and models to reduce implementation risk and engineering effort
  • Optimally partition functions between software and hardware with simulation and analysis tools
  • Support for the latest wireless communications standards, including both TDD and FDD modes for the 3GPP LTE standard
  • Fastest time-to-results for algorithm design with fixed-point simulation 20-200x faster than OSCI SystemC reference simulator
  • Drive verification from a single high-level model with C synthesis and eliminate re-coding & re-verification effort
  • Automated and unified development of application-specific processors(ASIPs), programmable accelerators and software development tool chain


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