The LTE Physical Layer Simulation Library provides unmatched increase in productivity for wireless physical layer system design. It can be used by network operators for investigation of system performance for scenarios specified in the standard as well as in corner cases relevant to optimizing network performance and cost.
Synopsys® Processor Designer is an automated, application-specific embedded processor design and optimization environment that slashes months from processor hardware design time and from the creation of application processor-specific software development tools.
SPW is the fastest path from innovation into implementation for digital signal processing systems, applying a model-based design approach.
System Studio is the high performance model-based algorithm design and analysis tool, combining unmatched simulation performance and highest modeling efficiency, plus industry's best integration into the implementation design and verification flow. Algorithm design is an essential task in signal processing applications such wireless telephony as, multimedia codecs, DSL and cable modems.
|Synphony C Compiler|
Synphony C Compiler is a high-level synthesis tool that provides an automated path from C/C++ in to silicon hardware. Using Synphony C Compiler, design teams can describe algorithms in high-level C/C++ and the quickly create optimized RTL implementations for FPGA or ASIC.
|Synphony Model Compiler|
Synphony Model Compiler (SMC) is a high-level synthesis tool that supports model-based design environments such as Simulink/MATLAB from the Mathworks. The Synphony high-level IP model library allows algorithm and hardware engineers to quickly create synthesizable fixed-point, multi-rate algorithms in a familiar, high-level design environment. Then the SMC high-level synthesis engine can be used to create an optimized RTL implementation of these algorithms for ASIC or FPGA.