|The fixed and the finite: QoR in FPGAs |
There is an intriguingly amorphous term in FPGA design circles lately: Quality of Results, or QoR. Fitting a design in an FPGA is just the start - is a design optimal in real estate, throughput, power consumption, and IP reuse? Paradoxically, as FPGAs get bigger and take on bigger signal processing problems, QoR has become a larger concern.
Jul 22, 2013
|Gigahertz FFT Rates on a 500MHz Budget|
Today’s systems often present a massive amount of very fast data at the front end that needs to be sampled and decimated quickly, typical of a system with a lot of data channels in play like satellite radio or cable head-end systems. Sample rates run into the gigahertz range, putting them outside the range of FPGA clock speeds if the constraint is one sample per clock. In this article, learn how Synopsys’ parallel FFT IP implementation allows data to be sampled and processed faster.
Apr 23, 2013
|Multi-Gigahertz FPGA Signal Processing|
Design teams from Xilinx and Synopsys know the importance of creating parallel architectures to accelerate signal processing applications on FPGA devices. In this article, learn how an FPGA clocked at 500MHz can support FFTs with gigasample per second data throughput rates.
Mar 28, 2013
|Power-Area Tradeoffs for Parallel Signal Processing Architectures|
Engineers working on datapath designs for high-speed signal processing must create architectures to meet the application’s performance and power needs. Learn how some of Synopsys’ signal processing flows can create and explore parallel architectures to address this challenge.
Mar 28, 2013
|Using Parallel FFT for Multigigahertz FPGA Signal Processing|
Very high-speed fast Fourier transform (FFT) cores are an essential requirement for any real-time spectral-monitoring system. As the demand for monitoring bandwidth grows in pace with the proliferation of wireless devices in different parts of the spectrum, these systems must convert time domain to spectrum ever more rapidly, necessitating faster FFT operations. This article examines the design of a parallel FFT (PFFT) with runtime-configurable transform length, taking note of the throughput and utilization numbers that are achievable when using parallel FFT.
Feb 01, 2013
|Part 3: Experts at the Table: Pain, Abstractions and ESL|
This is the third of a three-part series. See description below.
Mar 01, 2011
|Part 2: Experts at the Table: Pain, Abstractions and ESL|
This is the second of a three-part series. See description below.
Feb 01, 2011
|Part 1: Experts at the Table: Pain, Abstractions and ESL|
System-Level Design sat down with Thomas Bollaert, product marketing manager for Mentor Graphics’ high-level synthesis product line; Johannes Stahl, director of marketing for system-level solutions at Synopsys; Ran Avinun, marketing group director for system design and verification at Cadence, and Brett Cline, vice president of marketing and sales at Forte Design Systems; What follows are excerpts of that conversation.
Jan 01, 2011