Synphony DSP Design and Implementation 

Faster, More Efficient ASIC and FPGA Hardware Development for DSP Algorithms 

Model-based design environments are popular for DSP algorithm design and exploration because they allow concise representation of behavior at very high levels of abstraction. These environments provide fast design capture and easy-to-use simulation and debugging tools. However, problems arise when the designer needs to translate the DSP design intent into hardware optimized for ASIC or FPGA implementation. Hand-coding RTL for DSP algorithms is very time consuming and error prone, and requires tedious re-verification of the design in the RTL domain. Furthermore, hardware architecture exploration for area/delay/power trade-offs is limited because of these difficulties. The Synphony Model Compiler solution addresses these problems by providing an easy and automated way to create ASIC and FPGA hardware from high-level models created in the Simulink®/MATLAB® model-based environment.

 

 
Synphony C Compiler reduces development time and cost by shifting the focus of image processing IP implementation from designing at the RTL to designing at the algorithmic level.


 
Synphony Model Compiler provides a synthesizable model library for the MathWorks®, Simulink®, and MATLAB® environments enabling users to generate C models for fast verification and RTL optimized for the target FPGA or ASIC technology

Synphony C Compiler Features

Compilation from untimed sequential C/C++ code
  • Higher abstraction and productivity over RTL hand coding
  • Simpler, easier way to create a working algorithm
  • Rapid architecture exploration from C/C++ model
  • Eliminate re-coding and re-verification steps
Multi-level Hierarchical Design
  • Better QoR
  • Larger designs
  • More control over results
Block-Level Hierarchical Clock Gating
  • Easier architecture exploration of power tradeoffs
  • Lowers over-all power consumption
Robust Verification Methodology
  • Faster verification using C-based flows
  • Generates System C models for PV, PV+T, and TLM-wrapped RTL simulation
  • Reduced risk with fewer re-verification steps

Synphony Model Compiler Features

Synthesizable Fixed-point High-Level IP Model Library
  • Eliminates writing of fixed-point models from scratch
  • Faster verification using high-level simulation environment
  • High level IP for wireless, communications, and digital multimedia applications
High-Level Synthesis Optimizations and Transformations
  • Automatic system-wide pipeline insertion scheduling and resource sharing
  • IP-aware micro architecture optimization
  • Automatic loop unrolling, scheduling and pipelining
  • Target-aware optimization for FPGAs and ASICs
Integrated ASIC Flow
  • Automatic generation of RTL constraints and scripts for Design Complier
  • Advanced timing estimation using Design Compiler
  • Rapid architecture exploration of speed, area and power tradeoffs
Integrated FPGA Flow
  • Automatic generation of RTL constraints and scripts for Synplify Pro / Synplify Premier
  • Advanced timing estimation using Synplify Pro / Synplify Premier
  • Optimized resource mapping to advanced FPGA devices such as hardware multipliers, MACS, adders, memories and shift registers
  • Enables FPGA-based prototyping
RTL Testbench Generation
  • Automatic generation of test vectors and scripts for RTL verification in VCS
C-Model Generation for Software Development and System Validation
  • Fast model creation for C-based verification
  • Begin software development earlier using virtual prototypes

Synphony C Compiler Benefits

Higher Design and Verification Productivity from C/C++ Models
Synphony C Compiler creates application accelerators from sequential, untimed C algorithms for complex processing hardware in video, imaging, wireless and security domains. With easy adoption and high capacity, our C synthesis solution enables automatically inferred parallelism, interfaces and block resource sharing versus other ESL synthesis flows that rely on SystemC for manual coding of parallelism, partitioning, and interfaces.

Architectural Power Exploration and Savings
The Synphony C Compiler can save >50% for some applications by automatically building clock-gating structures at the architectural level. The power savings are over-and-above what can be achieved with gate-level clock gating in downstream tools.

Robust Verification Methodology and Productivity
The Synphony C Compiler generates verification models at various levels in the high-level synthesis flow, including PV (Programmer’s view) and PVT Programmer’s view + timing) and TLM wrappers for the RTL to be verified in the original C/C++ model. This provides a much more automated and reliable verification flow that eliminates significant risk, effort, and time associated with re-coding and re-verification done in traditional flows.

Synphony HLS includes advanced timing and device-specific optimizations for a broad range of FPGA families from Actel, Altera, Lattice and Xilinx. This includes optimized mapping to hardware multipliers, memories, shift registers and other advanced hardware resources in today’s FPGA devices.

FPGA-Based Prototyping Methodology for Early Algorithm Validation
With Synphony HLS and Synopsys’ technology-leading FPGA-Based Prototyping solution, design teams can quickly create a pre-silicon prototype of their design and start high-performance algorithm validation and embedded software development much earlier in the design cycle.

C-model Generation for Early Software Development and Fast System Validation
Synphony HLS complements C/C++ implementation, verification and embedded software development flows by making C-model creation a natural byproduct of the development flow. Synphony HLS generates fixed-point ANSI-C models that can be used in a variety of system simulation environments and virtual prototypes including Synopsys’ Virtual Prototyping solution, System Studio, VCS and SystemC flows. Synphony HLS enables C-based verification and validation to start much earlier in the design cycle.



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