|High Throughput GSPS Signal Processing Using Synthesizable IP Cores|
This whitepaper illustrates how parallel processing synthesizable IP cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or reduce power with sub-linear increases in area.
Sunil Ashtaputre, Director of R&D, Synopsys; Baijayanta Ray, DSP IP Architect, Synopsys
|Integrating High-Level Synthesis Designs into SoCs with Less Effort and Risk|
High-Level Synthesis (HLS) has many benefits for integrated circuit design but also introduces challenges for integration into SoCs. This paper proposes solutions that improve HLS system integration by eliminating manual interface specification, reducing debug and allow system integration and verification tasks to be performed earlier. By enabling an HLS to SoC flow from a model-based design environment, these methods increase productivity and eliminate manual effort, errors and risk.
Chris Eddington, Sr.Technical Marketing Manager for High-Level Synthesis, Synopsys
|No Room for Error: Creating Highly Reliable, High-Availability FPGA Designs|
Designers of FPGAs for military and aerospace applications need to increase the reliability and availability of their designs. This is particularly true in the case of mission-critical and safety-critical electronic systems. This paper provides brief definitions of key concepts: mission-critical, safety-critical, high-reliability and high-availability. It then considers the various elements associated with the creation of high-reliability and high-availability FPGA designs including: FPGA design and verification flows, methodologies, processes and standards, architectural and algorithmic exploration, geographically distributed design teams, IP selection and verification, DO-254 compliance and much more.
Angela Sutton, Staff Product Marketing Manager, Synopsys
|C/C++ for Complex Hardware Design|
An increasing number of ASIC and FPGA designs are accelerating algorithms and applications directly in hardware (HW) circuits. These HW accelerator cores have become commonplace and are now a key part of product differentiation and the ability to meet market expectations in performance, cost and reliability.
However, the implementation and verification of hardware acceleration cores is very difficult, especially due to the growing complexity of standards in video, imaging, wireless, and other multimedia and communications applications. RTL methodologies for IC design and verification are struggling to address this complexity in terms of productivity, available resources and time-to-market.
Chris Eddington Director of Marketing,High-Level Synthesis
and System-Level Products,Synopsys, Inc.