Today’s designers need better ways to get complex algorithmic designs into high-quality FPGA or ASIC implementations. Synphony high-level synthesis (HLS) tools provide optimization technologies that deliver high quality of results while enabling rapid exploration of performance, area, and power. These tools provide an efficient and reliable path from algorithm concept to silicon and enable greater design and verification productivity. Synphony C Compiler supports HLS from C/C++, and Synphony Model Compiler provides high-level synthesis from the Simulink model-based design environment.
The videos found here highlight the features of Synopsys’ high-level synthesis solution that enable automated implementation and verification of your ASIC and FPGA designs from higher levels of abstraction while eliminating months of implementation and verification effort.
Synphony Model Compiler
Quickly create complex multi-rate algorithms that are synthesizable into optimized FPGA or ASIC implementations. (Length: 20 mins)
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