LTE/LTE-A Model Library Extended
Since December 2012, several new reference systems and associated models have been made available as part of the LTE/ LTE-A library. For further information, please refer to the LTE/LTE-A library data sheet.
LTE Closed Loop Downlink
The LTE Closed Loop Downlink reference system is a complete end to end baseband model for simulating eNodeB to UE communication including dynamic link control based on UE measurements. This model extends the LTE Release 8 Downlink model to include UE calculation of optimal transmission rank, precoding matrix index and channel quality indicator feedback. These measurements are fed back to the eNodeB for link adaptation allowing for changes in the number of transmission layers, selection of spatial multiplexing or transmit diversity, modulation format, coding rate and precoding matrix. Optimal choices for all of these quantities are selected for each subframe allowing for maximum throughput based on current channel conditions.
LTE-A Dual Layer Beamforming
The LTE Dual Layer Beamforming reference system is a complete end-to-end baseband model for simulating Downlink communication between eNodeB to UE using UE-specific De-Modulation Reference Signals (DM-RS) according to the 3GPP Release 9 Specifications. UE-specific reference symbols for the two layers are code-multiplexed using orthogonal codes to enable beamforming over two spatial layers to a single UE. Such a UE is configured for PDSCH transmission mode 8.
Additionally, this reference system includes an implementation of an algorithm allowing for Open Loop estimation of throughput when an HARQ feedback path is not available. This is particularly useful, when the transmission source is not able to receive an ACK/NACK signal from the receiver, denoting the success or failure in decoding a received subframe.
The receiver in this reference system does not assume the knowledge of timing and/or channel and includes algorithms to estimate those parameters. Random delay is added to the radio channel model to characterize the unknown timing.
LTE Rel. 8 Downlink with Practical Channel and Timing Estimation
This system is similar to the Practical LTE Rel. 8 Downlink Channel system except that it performs practical timing acquisition, in addition to practical channel estimation. Timing acquisition is done using the primary and secondary synch signals embedded in the transmitted waveform. Half frame boundaries are determined by detecting the primary synch signal in time domain. After converting the received signal into frequency domain, consecutive secondary synch signals are used to determine the start of the LTE radio frame.
LTE Downlink with ML Interference Cancellation
This system is similar to the LTE Rel. 8 Downlink Channel system, but it also includes an additional model for an interfering eNodeB. The MIMO receiver in this system includes an implementation of a Maximum Likelihood algorithm with Interference Cancellation (MLIC) to detect the data transmitted from the desired eNodeB in the presence of interference. The modulation-type used at the interfering eNodeB is assumed to be unknown and is estimated by the implemented MLIC algorithm.
LTE Uplink simple EVM
LTE uplink EVM calculation which includes:
- Phase and amplitude correction in the frequency domain
- Calculation starting at two points in the cyclic prefix
- Separate calculation for shared channel and reference signals
- Average EVM, peak EVM and per symbol EVM calculation
The simplified model doesn’t include timing or frequency correction.
New Video: LTE / LTE-A Model Library
This short video provides an overview of the LTE / LTE-A library. It gives insight into the overall structure of the library, its appearance within the SPW block-diagram based design canvas, and its modular structure which allows easy integration of customer-designed models. In addition to the models themselves, it covers the ready-to-use scripts that represent the 3GPP-compliant test cases, and how to efficiently simulate these test cases using the built-in multicore support. (After starting the video, please change the video quality to 1080p for the best viewing experience).
WCDMA/HSPA Library Extensions
The June 2013 release also features further enhancements to HSPA+:
- A chip rate equalizer has been added along with the standard RAKE receiver. Performance comparisons between both receivers therefore become very easy.
What's New in SPW and System Studio?
In June 2013, both SPW and System Studio have new releases available.
SPW 2012.12-SP1 (June 2013) release notes available for download from SolvNet. The release includes:
- New properties tab, improving speed and usability. It allows for a faster display of the parameters / ports table, and a faster selection of the block instances.
- Drawing time for large designs has been reduced significantly. Initially released with 2012.12 as a BETA feature for Linux only, drawing time for large designs is now fully released and available for Windows as well.
- Enhanced MATLAB interface, now supporting dynamically changing matrix and vector sizes.
- New installer which simplifies the overall installation process for Windows users.
- The HDS flow has been further enhanced to reduce the number of warnings when compiling the design with the latest release of Design Compiler.
System Studio 2012.12-SP1 (March 2013) and 2012.12-SP2 (June 2013) release notes available for download from SolvNet. The releases include:
- Enhanced MATLAB Import: importing a MATLAB function into System Studio is now easier than ever. The ccss_matlab and mat2ccss utilities allow the automatic creation of PRIM wrapper models, mapping the MATLAB function arguments to ports, parameters, or state variables of the generated wrapper model. Additional data types such as matrices and vectors of (complex) double, float or int are also useable with the MATLAB function.
- New training module available: Using System Studio with MATLAB. As with all training modules, this is shipped with the release, so no separate download or installation is required.
- SDS models now come with data type support for 64 bit.
- Struct Arrays can now be used as a data type of a model parameter.
- Function-like PRIM macros are now available. The main difference to an external C/C++ function is that these macros are transparent for the simulator, so that simulation code optimizations can apply.
- RTL co-simulation with VCS has been further improved, supporting the seamless import of mixed VHDL/Verilog designs.
- SystemC model export and import to VCS now support SystemC 2.2 as well as SystemC 2.3 as supported by VCS 2012.09 – 2-13.06.
- SystemC model export and import to Modelsim 10.2 requires a specific runtime library that is built with the Modelsim header files. This library is now available for SystemC 2.2
- Native support for CDF models: System Studio now supports SPW's CDF (C Data Flow) modeling style, allowing for native import of CDF libraries. CDF models can be instantiated, connected and parameterized in System Studio DFG (data flow graph).
Events & Webinars
New Webinar recording: Conquering HSPA+ Modem Design – Accelerating Algorithm Design and IP Verification (jointly with Interdigital)
Abstract: As UMTS has expanded to greater capacity and data rates with HSPA+, its ability to meet market demands has been extended and the technical challenge to develop conforming IP has increased. InterDigital has adopted a design flow utilizing SPW to enable quick validation of prototype algorithms that can be readily measured against 3GPP requirements. The constituent algorithms are integrated into a complete PHY-layer SPW simulation environment complete with surrounding NodeB and RF aspects to gain confidence in end-to-end performance characteristics. Additionally, this design flow reuses the same simulation models to verify the IP thus ensuring that the end product meets the requirements. This webinar will describe this design flow and provide an introduction to InterDigital’s HSPA+ modem IP.
- Recorded webinars
- LTE-A Modems Coming to Life (jointly with Rohde & Schwarz)
Synopsys and Rohde & Schwarz teamed up for this seminar to discuss the steps needed at the different stages of the LTE/LTE-A modem design process and how these steps can be integrated into a complete design and verification flow.
- LTE-A Physical Layer Design and Simulation
Introduction to the LTE-A standard (Rel. 10), explaining the main enhancements over LTE Rel. 8 and their implication on the overall system complexity. Synopsys' LTE-A baseband reference library, a standard-compliant physical layer reference library verified in collaboration with Rohde & Schwarz, is used to demonstrate the new features of LTE-A, its complexity and operation.
- LTE Physical Layer Design: Basics
Overview of the LTE Standard, LTE simulation library and Synopsys SPW algorithm design tool
- LTE Physical Layer Design: Optimization
LTE physical layer design and how design choices can impact implementation and performance
- LTE Physical Layer Design: Synchronization
Learn more about some of the features of the LTE User Equipment (UE) acquisition and synchronization process.