Algorithm Design eUpdate, April 2011 

Contents: 


What’s New in SPW and System Studio?
Since the last Algorithm Design eUpdate in November 2010 there have been new releases of both SPW and System Studio. You can find the software as well as the detailed release notes in SolvNet. Some release highlights are below:

SPW 2010.12 (December 2010, release notes available for download from SolvNet):

  • First Synopsys release of SPW featuring the Synopsys standard licensing mechanism
  • New packaging: most of the SPW model libraries are now included with SPW as a default option
  • LTE library enhancements, including support for TD-LTE in addition to FDD , and faster CDF models
  • VCS co-simulation
  • Integration with Synplify Pro® synthesis as part of the FPGA flow
  • Enhanced Rapid Hardware Implementation Flow

System Studio 2010.12 & 2010.12-SP1 (December 2010 / March 2011, release notes available for download from SolvNet)

  • The LTE library is now also available in System Studio with standard compliant end-to-end systems, featuring TD-LTE as well as FDD-LTE
  • Reduced time to simulation, significantly reducing the time it takes to start a simulation after making local changes to the design
  • MIMO model library – generic building blocks for the development of advanced communication concepts, taking advantage of matrix and vector data types (This includes example systems and generic channel models)


Customer Success: Stellamar
Stellamar has pioneered the development of a new Digital ADC (analog-to-digital converter) technology that can be implemented in a digital silicon technology without using any of the analog IP blocks traditionally used for ADC designs. This technology reduces the design cycle time and cost of ADCs integrated in ASICs, and can be implemented in fully digital microchips such as FPGAs avoiding the use of costly external ADCs and saving board space.

SPW was used extensively to model, simulate and verify the algorithm for the ADC. Once verified, Stellamar used SPW hardware design system (HDS) to generate synthesizable RTL code for a power and area optimized fully digital synthesizable ADC.

Read the complete Stellamar Success Story


User Tip: Debugging Algorithm Simulations for Memory Problems
Memory problems are common when running complex system simulations. They might only become visible when they cause high memory consumption, non-deterministic simulation behavior or even simulation crashes after millions of samples have already been processed. Often the root cause of these types of problems is difficult to detect and fix.

The tool support in System Studio along with the methodology presented in the “Advanced Debugging” training module gives you a proven and successful path to fixing these memory-related design bugs. The training module gives you step-by-step instructions on how to identify the root cause of the problem and also includes lab exercises where you can practice the techniques on well prepared examples. This training module, as well as all other modules, is available from the Help menu in System Studio.


Events & Webinars

April 19th, 2011

Webinar: Performance Validation of Advanced LTE MIMO Receivers Implemented with Xilinx LogiCORE IP
Overview:
Learn how Xilinx MIMO IP can help you implement advanced MIMO receivers for LTE base stations (eNodeB) with up to 4 Multi-User MIMO codewords and validate its performance in the Synopsys LTE library.
Click here to view a recorded version of this webinar

Webinar: Killing the Pain of Fixed-Point Design
Overview:
Learn how to efficiently convert floating-point into fixed-point algorithm specifications using an easy flow applicable to a wide range of signal-processing applications.
Click here to view a recorded version of this webinar

May 5th, 2011

Closing the Verification Gap: Integrating Algorithm and RTL Verification for Signal-Processing Applications
Overview:
Learn how to take advantage of behavioral models for RTL verification to create an integrated signal-processing verification flow from algorithm concept to RTL.
Click here to register

Recorded webinars, addressing the LTE standard



NewsArticlesDatasheetsSuccess StoriesWhite PapersTechnical PapersWebinarsVideosNewsletters