| SoC Architects Face Big Challenges |
While the geometries of advanced node processes such as 28nm and below may not greatly impact SoC architectures, the complexity enabled by the leading edge brings intense challenges all the same.
Jan 31, 2013 |
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| 30 years of DSP: From a child's toy to 4G and beyond |
Dec 18, 2011, marked the 25th anniversary of EDA provider Synopsys Inc, which has been both witness to and participant in the evolution of signal processing.
Aug 27, 2012 |
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| Early Optimization of Multicore SoC Architectures Using System-level Design Methods and NoC Interconnect Technology |
Learn how one can use system-level design methods at the earliest stages of SoC design to determine the optimal interconnect configuration that meets a set of performance goals and system constraints. With a system-level environment like Synopsys Platform Architect and configurable SoC interconnect IP like Arteris FlexNoC, it is possible to quickly create and run multiple simulations that explore and optimize possible configurations.
Aug 20, 2012 |
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| SoC Platforms Gain Steam |
Platforms are attracting far more attention from makers of SoCs because they are pre-verified and can speed time to market, but the shift isn't so simple. It will spark major changes in the way companies design and build chips, causing significant disruption across the entire SoC ecosystem.
Jul 26, 2012 |
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| Software Agnostic Approaches to Explore Pre-silicon System Performance |
A new modeling methodology is proposed to improve performance validation at an early stage in the design cycle of systems dedicated to handheld devices. Hardware models are typically available early in the chipset development cycle, but software, such as multimedia applications, may not be developed until after the ASIC is designed. An alternative source of simulation stimulus must be found so that hardware models can be exercised in the absence of such software. This paper describes three approaches that overcome this dependency and enable the validation of application processor performance at the architecture stage of silicon design: high-level software models, trace-driven characterization, and statistical traffic models. Correlation between actual measurements and simulation outputs demonstrates that these methods provide adequate accuracy for performance validation.
May 22, 2012 |
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| Virtual Platforms: Breaking New Grounds |
The case for developing and using virtual platforms (VPs) has now been made. If developers of complex HW/SW systems are not using VPs for their current design, complexity of next generation designs demands for their adoption. This paper summarizes a special session focused on the latest applications and latest use cases for VPs. It gives an overview of where this technology is going and the impact on complex system design and verification.
May 22, 2012 |
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| IEEE Approves Revised IEEE 1666™ "SystemC Language" Standard |
IEEE announced that the IEEE Standards Association (IEEE-SA) Standards Board has approved a revised version of the IEEE 1666™ "Standard SystemC Language Reference Manual," which specifies SystemC, the high-level design language used in the design and development of electronic systems. The new version of IEEE 1666 encompasses many enhancements, notably the support for transaction-level modeling (TLM), a critical approach to enable higher level and more efficient design of complex integrated circuits (ICs) and system-on-chips (SoCs).
Nov 10, 2011 |
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| Platform Architect MCO is EDN Hot Product of 2011 |
Synopsys' Multicore Optimization Technology is EDN's hot product of 2011. This technology is meant for performance analysis and early definition of multicore system architectures in SystemC. With Multicore Optimization Technology, users of of Platform Architect can capture HW/SW performance models of multicore system architectures in the early concept phase for robust performance measurement and trade-off analysis, months prior to software availability.
Nov 08, 2011 |
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| Optimizing Multicore System Performance |
Multicore Optimization technology, part of Platform Architect, enables design teams to more accurately predict system performance using SystemC months before software is available.
Jun 22, 2011 |
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| Using SystemC to build a system-on-chip platform |
How Texas Instruments' designers used the SystemC hardware design language to do performance modeling when creating both the company's OMAP-2 platform and the devices based on it.
Feb 02, 2011 |
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| Using the application modeling and mapping methodology for system-level performance analysis |
This article describes our experiences using the Application Modeling and Mapping methodology (AMM) based on commercial tooling from Synopsys. This methodology is valuable at the technical and organizational level for investigating the feasibility of new electronic products.
Sep 26, 2010 |
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| Get an optimized flow on an AMBA-based design |
CoWare announced the availability of a new interconnect and memory-subsystem performance optimization design flow for its Platform Architect product.
Jun 15, 2009 |
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| ESL Methods for Optimizing a Multi-media Phone Chip |
Our team is chartered to validate and optimize the architecture of our NXP mobile phone chips. This is a very challenging application domain, as an ever increasing set of multi-media and wireless communication functions need to be integrated into one SoC.
May 27, 2008 |
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