VCS Verification Library
The VCS Verification Library, containing DesignWare® VIP, provides a broad portfolio of design-proven, standards-based VIP to dramatically speed testbench development time and achieve functional coverage goals faster. It now supports the constrained-random, coverage-driven methodology defined in the Verification Methodology Manual (VMM) for SystemVerilog. In addition, the verification IP supports Native Testbench in VCS to deliver up to 5X improvement in runtime performance.
The VCS Verification Library easily integrates Verilog, SystemVerilog, VHDL and OpenVera® testbenches. Learn More...