| Synopsys Users Group (SNUG) Papers |
 | VMMing a SystemVerilog Testbench by Example
Ben Cohen - VhdlCohen Publishing,
Srinivasan Venkataramanan, Ajeetha Kumari – Independent |
 | Verifying a Networking ASIC using a SystemC Reference Model and a SystemVerilog Testbench
Amit Malhotra - Cisco Systems,
Angshuman Saha, Sanjaya Sharma – Synopsys, Inc. |
 | SystemVerilog Assertions are for Design Engineers Too!
Stuart Sutherland - Sutherland HDL, Inc.,
Don Mills - LCDM Engineering |
 | SystemVerilog Constraints for Assertion-based Formal Verification
Hanif Perwad - SGI,
Mandar Munishwar - Synopsys, Inc. |
 | Using SystemVerilog Testbench for High Level Behavioral Modeling of a SIMD Processor Design
Shankar Govindaraju, Jayanto Minocha, David Dobrikin, Kevin Rich - Transmeta Corp. |
 | PSL |=> SVA: A Case Study in The Use of Assertions, and The Power of SVA
Al Czamara - LOA Technology |
 | Creating a VMM Compliant Verification Plan
Ambar Sarkar - Paradigm Works |
 | SystemVerilog Saves the Day-the Evil Twins are Defeated! unique and priority are the new Heroes
Stuart Sutherland, Sutherland HDL, Inc. |
 | The Verilog PLI is Dead (maybe) -- Long Live the SystemVerilog DPI!
Stuart Sutherland, Sutherland HDL, Inc. |
 | Integrating SystemC Models with Verilog and SystemVerilog Models Using the SystemVerilog Direct Programming Interface
Stuart Sutherland, Sutherland HDL, Inc. |
 | Modeling FIFO Communication Channels Using SystemVerilog Interfaces
Stuart Sutherland, Sutherland HDL, Inc. |
 | Using SystemVerilog for IC Verification
Mikhail Noumerov, Motorola GSG-Russia
Lyubov Zhivova, Motorola GSG-Russia |
 | Object Oriented Testbench Development with VeraHVL and SystemVerilog Assertions (SVA)
Glenn P. Dunlap, Sigmatel |
 | The Bumpy Road of Progress: Transitioning to a SystemVerilog-based Simulation Environment for Embedded ASIC Verification
Won Rhee, Agilent Technologies |
 | A Unique Functional Coverage Flow using SystemVerilog and NTB
Richard Raimi, ARM, Inc.
Dennis Strouphauer, Synopsys, Inc. |
 | Verification of a Mixed Signal ASIC Using SystemVerilog with MATLAB and the DPI
Ron Shipp, Synopsys Professional Services
Rene Abraham, Midas Communications Technology
Rabeek Mohamed, Midas Communications Technology |
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