SystemVerilog for Design

Benefits

• 2 to 5 times less code to capture same functionality
• Strong type checking
• "Same semantics" interpretation by all tools
• Evolutionary change to better methodology

The SystemVerilog language brings significant productivity benefits to design engineers. Its advanced design constructs yield more compact RTL code, typically a two-to-five times reduction in lines of RTL. Fewer lines of code translate to fewer coding errors and increased designer productivity. The SystemVerilog language also eliminates inconsistent interpretations between simulation and hardware implementation. This clarifies intended design behavior and accelerates equivalency checking.

2-5X Less Code with SystemVerilog

Synopsys' Galaxy™ Design Platform offers a complete SystemVerilog implementation flow, including Design Compiler® for RTL synthesis, Leda® for design checking and the Formality® equivalence checker. Formality’s newly available native SystemVerilog parser eliminates the use of language conversion, improving both accuracy and time to results.

White Papers

SystemVerilog Assertions are for Design Engineers Too! Stuart Sutherland - Sutherland HDL, Inc., Don Mills - LCDM Engineering Modeling with SystemVerilog in a Synopsys Synthesis Design Flow Using Leda, VCS, Design compiler and Formality Stuart Sutherland - Sutherland HDL, Inc..

For More Information

To learn more about Synopsys SystemVerilog design solutions, please contact: systemverilogdesign@synopsys.com