Hands-on Training for Synopsys Tools and Methodologies 

Learn from the experts. Our comprehensive catalog of hands-on classes shows you how to make the most of your investment in Synopsys tools. Choose among the delivery options--Public Classes delivered at a Synopsys Training Center around the world, Private Workshops at your site, the live Synopsys Virtual Classroom, and self paced On Demand training--that best meet your time, budget and project needs.

  • Verification
  • Functional Verification Courses 

Power-Aware Verification with VCS-NLP and UPF
A hands-on introduction to use VCS-NLP to run and debug power-aware simulations on RTL code instrumented with power intent defined using IEEE-1801 (aka UPF).

SystemVerilog Assertions
This class teaches the key features of the SystemVerilog Asssertion language and its use in VCS, including how to create reusable, scalable assertions and assess the effectiveness of your testbench.

SystemVerilog Testbench
This workshop provides a hands-on introduction to the SystemVerilog language to verify a device under test using VCS with object-oriented methodologies targeting coverage-driven constrained-random test environments.

SystemVerilog Verification using UVM 1.2
In this course, you will learn how to build EDA industry standard UVM 1.1 and UVM 1.2 testbenches. It is recommended that you take the SystemVerilog Testbench workshop before this class.

  • RTL Synthesis
  • Design Synthesis Courses 

Design Compiler
This course covers the ASIC synthesis flow using Design Compiler Topographical / Graphical to generate a gate-level netlist which will result in acceptable post-placement timing and congestion.

Design Compiler 2: Low Power
This seminar based course covers Low Power Synthesis using Design Compiler Topographical with Power Compiler by using traditional (single voltage) and UPF based (multi voltage, multi supply) power optimization techniques.

DFT Compiler
In this course you will learn to use DFT Compiler to perform RTL and gate-level DFT rule checks, fix DFT DRC rule violations, and insert scan using top-down and bottom-up flows.

SystemVerilog for RTL Design
In this course, you will learn how to achieve high quality of results for your RTL design using SystemVerilog. It is assumed that you are versed in Verilog and want to improve your RTL coding efficiency with SystemVerilog.

  • Sign-Off
  • Design Sign-Off Courses 

PrimeTime PX: Signoff Power Analysis
This workshop will show you how to use PrimeTime PX to effectively analyze peak power and average power in both UPF and non-UPF flows.

This course covers a recommended Static Timing Analysis (STA) methodology using PrimeTime to generate STA reports that are based on validated timing constraints.

PrimeTime SI
The PrimeTime SI course teaches the techniques to increase the precision of your STA while taking into account crosstalk effects.

In this course you will learn how to use TetraMAX® to perform ATPG on a post-layout chip netlist scan design.

  • Physical Implementation
  • Design Implementation Courses 

IC Compiler II: Block-level Implementation
Learn to use IC Compiler II to run a complete Place and Route flow on Block-level designs. The flow covered within the workshop addresses the main design closure steps for multi-voltage designs, with multi-corner multi-mode (MCMM) timing and power challenges.

IC Compiler II: SoC Design Planning
Learn to use IC Compiler II to perform chip-level hierarchical design planning (floorplanning) on multi-voltage (UPF) "System-On-a-Chip" (SoC) designs. The flow includes handling "multiply-instantiated blocks" (MIBs), voltage areas, black boxes, timing budgets and power network design using "Pattern-based Power Network Synthesis" (PPNS).

IC Compiler Block-Level Implementation
Learn to use IC Compiler to perform data setup for MCMM optimization, placement, CTS, routing and design-for-manufacturability on non-UPF block-level designs with existing floorplans.

IC Compiler SoC Design Planning
Learn to use IC Compiler to perform chip-level hierarchical design planning on large multi-voltage (UPF) “system-on-a-chip” (SoC) designs. The flow includes handling black boxes, “multiply-instantiated macros” (MIMs), and voltage areas.

  • DFM
  • DFM & TCAD Courses 

Basic TCAD Sentaurus
This course will introduce users to basic concepts of how to use Synopsys’ TCAD tools.

  • FPGA Design
  • FPGA Implementation Courses 

Synplify Pro & Premier
The course will familiarize new students with the FPGA design flow utilizing features of the Synplify Pro product.

This course introduces concepts on full-speed hardware debugging using the Identify toolset which provides an "embedded HDL analyzer".

This course introduces concepts on ASIC prototyping using the Certify ASIC Prototyping tool.

Synphony Model Compiler
This course shows users the Synphony Model Compiler design flow including model creation, implementation and architectural exploration.

Public Classes
Instructor-led training is offered at Synopsys’ global training centers. Classes include both lecture sessions and the opportunity to practice what you learn in hands-on labs. Course Calendar

Private Classes
All standard Synopsys classes can be offered as private workshops for groups of 8 or more students. We also offer customized training designed to meet the unique needs of your design team. An expert Synopsys instructor will deliver your private class at a Synopsys training facility, at your location or via Webex®--whichever is most convenient for you. Contact us

On-Demand Training
Pre-recorded, self-paced training modules on a range of topics, including the latest tool features, design methodologies, and how to deal with common support issues are available on SolvNet. (a SolvNet userID is required).