Advanced Algorithm Implementation with Synplify DSP™   

 

Overview
This course first introduces new users to the Synplify DSP tool. Designers can take this course at their own pace and enjoy the online version of this class. Comprehensive notes complete the information displayed on each page. This course is powered by Vitalect.

Objectives
The course will familiarize new students with the Synplify DSP design flow including model creation, implementation and architectural exploration, enabling them to actively create designs using the Synplify DSP product. The course then expands on these concepts to focus on more complex modeling and implementation features.

Audience Profile
Designers who wish to quickly capture complex algorithmic behavior by using a high-level modeling library combined with a powerful DSP synthesis engine.

Prerequisites
Familiarity with DSP functions and applications, experience in Verilog or VHDL design and logic synthesis.

Course Outline
  • Flow Overview
  • Signal Date Types
  • Vector Support
  • Multi-rate Modeling
  • Architectural Synthesis
  • Micro-architectural Optimizations
  • Retiming
  • Folding and Multi-Channelization
  • Advanced Features and IP Functions

Synopsys Tools Used
  • Synplify DSP

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