|The New Economics of Verification|
A more intelligent approach to verification can help design teams control the rising cost of chip design, according to Manoj Gandhi, senior vice president and general manager of Synopsys' Verification Group.
Sep 13, 2010
|The Growing Software Challenge - From Stack to SMP|
Building a system now includes software, but defining the software stack is a mounting challenge for engineers. What used to be almost exclusively drivers now includes RTOSes and OSes, executable files, middleware, firmware, IP, embedded software and applications.
Aug 26, 2010
|Experts at the table: System-level verification |
Summary: System-Level Design sat down to discuss issues in system-level verification with Frank Schirrmeister, director of product development in Synopsys' solutions group; Donald Cramb, director of professional services at Eve; Patrick Sheridan, director of marketing at CoWare, and Scott Sandler, president of SpringSoft USA. What follows are excerpts of that conversation.
Jul 22, 2010
|System Level Software Centric Power Debugging using Virtual Prototypes|
Battery life has become the Achilles heel for the success of mobile software platforms, such as Android. This article outlines how Virtual Prototypes (VPs) provide all the necessary elements for a debug solution that can spot and remove power related defects from software.
Jul 20, 2010
|Generating AMD microcode stimuli using VCS constraint solver|
In this article, we explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver. We present and analyze the method and discuss its effectiveness in today’s verification environment.
Jul 14, 2010
|TLM-Based Verification Finds Strength In Standards|
In the verification realm, new and emerging standards are behind the broadening acceptance of transaction-based verification methodologies. Standards like OSCI's TLM (transaction-level modeling) 2.0 and Accellera's Standard Co-Emulation Modeling Interface (SCE-MI) have led to a groundswell of interest in transactions. Also, flows are now using hardware acceleration and emulation to give transaction-based verification a turbo boost in speed.
Jun 22, 2010
|SaberRD – Desktop Environment for Power System Design |
The design of modern power systems demands modern tools for modeling and simulating physical behavior. The March 2010 release of the Saber Products marks the introduction of SaberRD, an intuitive desktop environment for designing and simulating complex power systems.
Jun 20, 2010
|Virtual Prototypes for Software-Dominated Communication Systems Designs|
In a variety of application domains like wireless, multimedia, networking, and automotive, it has become more and more difficult to provide silicon solutions without the associated software executing on the hardware. Not only has software become the key functional differentiator in many areas; its development cycle now determines the overall project success.
Jun 01, 2010
|Virtual prototyping pushes the fast forward button for software development|
An introduction to how virtual prototyping takes a pair of scissors to development time and costs. Developing software for hardware prototypes that aren’t yet available has always been a complex, time-consuming task with inherent risk. The arrival of effective, easy-to-use development tools was a significant first step toward developing code faster with fewer bugs.
May 17, 2010
|Attacking Constraint Complexity: Verification IP Reuse|
his two-part article series looks at a scalable constraint methodology and provides an overview of some of the key constraint optimization challenges and strategies of concern to verification engineers. Part 1 of this article series focuses on verification IP reuse—detailing how a solver typically interprets constraints and providing a case study focused on a constraint-driven performance optimization strategy with respect to the flexible packet parser of a hypothetical networking ASIC.
Mar 02, 2010
|2010 Will Change The Balance In Verification|
What will 2010 bring for verification and system-level design? The semiconductor "beasts" that need to be verified are getting more and more complex. These beasts are developed at smaller technology nodes, and with the declining number of design starts. Programmability plays a significant role, both in ASIC and ASSP designs, since users have to deal with more and more processors.
Jan 08, 2010
|Saber Worst-Case Analysis|
From systems to silicon, designers are using simulation to assure higher levels of reliability in their products. The December 2009 release of the Saber products features powerful new capability for performing Worst-Case Analysis on power electronic and multi-domain circuits, taking designers beyond the limitations of traditional WCA techniques.
Jan 01, 2010
|Taking power analysis to the transistor level for a full chip|
Neither functional simulation nor conventional power estimation can catch some major issues in power consumption for low-power designs. Large-area mixed-signal simulation may be the right answer.
Dec 04, 2009
|Accelerating Embedded Software Development with Rapid Prototyping|
In this article Neil Songcuan, Technical Marketing Manager at Synopsys, discusses the challenges faced by Embedded Software Developers and how rapid prototyping can help them to accelerate development, maintain cost effectiveness and retain a competitive advantage in today's environment.
Oct 05, 2009
|Verification alive and well at SoC virtual conference|
During the first EE Times System-on-Chip Virtual Conference, a panel on verification challenges raised pressing issues in the areas of cost, startups, impact of electronic sytem level (ESL) design, virtual plattforms and functional verification as a methodology.
Sep 17, 2009
|SystemVerilog and VMM Overcome WiMAX Verification Challenges|
SystemVerilog and VMM-based environment help achieve first pass silicon success by performing smarter verification quicker.
Aug 05, 2009
|Software-to-silicon verification @ 45nm and beyond|
Chip and system developers once considered verification as a secondary activity following the main challenge of design, with the "Designer" playing the central role in a design's success. This notion is firmly turned on its head today, as verification is the biggest component of chip hardware development budgets, schedules, staffing and risk.
Jul 20, 2009
|Chip-verification and design flow focuses on low power|
The latest generation of Synopsys' Discovery verification platform upgrades the offering with new multicore simulation technologies, native design checks and low-power verification capabilities.
May 01, 2009