|FinFET Technology – Understanding and Productizing a New Transistor From TSMC and Synopsys|
This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this solution include comprehensive FinFET profiling without impact to design tool runtime and proven, verified IP availability. The TSMC 16-nm FinFET solution will ensure mutual customers swiftly move to building the next generation SoCs.
Jason S.T. Chen, TSMC; Andy Biddle, Synopsys
|Designing with FinFETs: The Opportunities and the Challenges|
FinFET devices have a significantly more complex topology than planar FET devices. In addition, their design features and characteristics are quite different, creating many questions for designers. This paper discusses new design opportunities to optimize the design metrics of performance, power, area, cost, and time to market and the new design challenges.
Jamil Kawa, R&D Director, Synopsys
|Accelerating 20nm Double Patterning Verification |
This whitepaper presents the key concepts of DPT compliant design and demonstrates how new signoff technology in IC Validator makes it possible to ensure 20nm manufacturing compliance. Recognizing that the designer productivity necessary cannot be achieved alone by point-tool enhancements and post-processing techniques, the paper outlines advances in In-Design physical verification within IC Compiler.
Paul Friedberg, CAE, Synopsys; Stelios Diamantidis, Product Marketing, Synopsys
|20nm and Beyond white paper |
The consumer’s insatiable demand for greater performance, a shrinking form factor and extended battery life, all while continuing the trend for lower end user cost is the driving force behind the semiconductor industry’s rapid evolution to ever smaller process geometries.
Andy Biddle, Product Marketing Manager, Galaxy Implementation Platform, Synopsys