|DAC 2016 Custom Compiler Lunch Videolog: Cutting Layout Tasks from Days to Hours|
FinFET devices have added significant complexity to the design flow, and many companies are seeking new solutions for custom design. Custom Compiler’s pioneering visually-assisted automation can cut layout tasks from days to hours.
On June 7, 2016, Synopsys hosted a Custom Compiler Luncheon at DAC. At this event, attendees heard users discuss their experiences with custom design challenges and how they have deployed Custom Compiler to improve their custom design productivity for both FinFET and established nodes.
GSI, Samsung, STMicroelectronics, Synopsys IP
|DAC 2016 Circuit Simulation Lunch Videolog: Robust AMS Design Verification at Advanced Nodes|
On June 6, 2016, Synopsys hosted a Circuit Simulation Luncheon at DAC. At this event, attendees heard Industry leaders from Oracle, Samsung and STMicroelectronics discuss their design verification challenges that stem from cutting-edge advanced technologies and increasing design complexity in memory, analog, and mixed-signal applications, and how they overcome such challenges by using Synopsys AMS circuit simulation solutions to ensure design robustness.
Sam Lo, Hardware Development Manager, Oracle; Zach Coombes, CAD Engineer, Samsung; Atul Bhargava, Sr. Staff Engineer, STMicroelectronics
|Designing 7-nm IP, Bring It On Moore!|
In keeping with Moore’s Law, discover how Synopsys is developing 10nm/7nm IP for SoC designs. Learn how tradeoffs are made in electrostatics, leakage, pattern, manufacturability and transistor performance to meet PPA requirements. See how quantum effects impact FinFET designs in terms of fin width, fin height and anything that impacts bandgap. Technology can be scaled to 7nm, bringing performance and power improvements.
Navraj Nandra, Sr. Director of Marketing, Synopsys
|SNUG 2016 Custom Compiler Videolog: Cutting Layout Tasks from Days to Hours |
On March 31, 2016, Synopsys hosted a Custom Compiler Lunch ‘n’ Learn at SNUG Silicon Valley. At this event, attendees heard industry leaders share their experiences using the new Custom Compiler visually-assisted automation to meet the challenges of FinFET custom design, and discuss how it improves their custom design productivity.
AMD, STMicroelectronics, Synopsys IP
|Introducing Custom Compiler Visually-assisted Automation|
Antun Domic, Executive VP and GM of the Design Group unveils Synopsys' next-generation custom design solution.
Custom Compiler brings new levels of productivity to FinFET layout by employing visually-assisted automation technologies that speed up common design tasks, reduce iterations, and enable reuse.
Antun Domic, Executive VP and GM of the Design Group, Synopsys
|Successfully Designing with FinFET|
This video was taken during the 25th annual Synopsys’ User Group (SNUG) in Silicon Valley on March 23, 2015 where attendees had the opportunity to hear from a panel of industry leaders who shared their FinFET design experiences and successes.
Tom Arns, Altera; Mamta Bansal, Qualcomm; Kelvin Low, Samsung; Anwar Awad, Synopsys
|Addressing 16nm FinFET Challenges to Tapeout a 50M+ ARM® Cortex®-A57 processor-based SoC using Synopsys IC Compiler™|
In this video, you’ll hear briefly about Synopsys’ participation at ARM TechCon 2014 followed by a Synopsys and HiSilicon joint presentation on HiSilicon's successful tapeout of their first production SoC in 16nm FinFET technology.
Kelvin Chen, Principle Engineer, COT Department, HiSilicon
Muming Tang, Staff Applications Consultant, Synopsys
|Physical IP Development on FinFET - There's Nothing Planar About It! (12:30-2:00)|
This video discusses the FinFET characteristics of physical IP design and how they differ from planar devices. It will describe the impact FinFETs have on existing circuit designs and layout topologies for widely used IP such as DDR, USB, PCI Express, embedded memories and logic libraries.
Navraj Nandra, Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP, Embedded Memories and Logic Libraries, Synopsys
|Designing IP for FinFET Technology|
FinFETs are emerging as the device technology of choice at advanced nodes. This introduces new design challenges for IP development, which require knowledge of and experience in designing with FinFETs to ensure design success. This video describes the benefits and challenges of transitioning from planar to FinFET technologies and how IP plays a significant role in this transition.
Jamil Kawa, R&D Director, Synopsys
|Industry Experts Discuss FinFET Technology and Early Experiences|
During SNUG 2013 in Silicon Valley, a panel of experts from foundry and semiconductor companies joined Synopsys in a discussion about their early experiences with FinFET Technology. Watch this video to learn about the different perspectives, the challenges this new technology introduces and the solutions they explored.
Dr. Antun Domic, Synopsys; Joachim Kunkel, Synopsys; Subramani Kengeri, GLOBALFOUNDRIES; Michael Campbell, QUALCOMM; Anil Jain, Cavium;
|Trends in Silicon Technologies - Enabling 20nm for Multimedia Convergence|
On June 4, 2012, Synopsys hosted an IC Compiler luncheon during the Design Automation Conference (DAC) where Mr. Philippe Magarshack of STMicroelectronics spoke about enabling 20nm for multimedia convergence.
Philippe Magarshack, Corporate Vice President, Design Enablement & Services, STMicroelectronics
|Designing for GLOBALFOUNDRIES 20nm Technology and Beyond - Winning Through Collaboration|
Dr. Joerg Winkler is a Fellow at GLOBALFOUNDRIES in Dresden, Germany working within the Design Enablement group. On June 4, 2012, Synopsys hosted an IC Compiler luncheon during the Design Automation Conference (DAC) where Dr. Winkler spoke about designing at 20nm technology and beyond.
Dr. Joerg Winkler, Fellow, Design Enablement , GLOBALFOUNDRIES
|GLOBALFOUNDRIES and Synopsys Discuss 20nm enablement|
The 20nm process node poses a number of new, complex design tool challenges. Synopsys’ Andy Biddle asks GLOBALFOUNDRIES’ Richard Trihy how the company plans to enable its customers for this technology.
Richard Trihy, director Design Methodology,
Andy Biddle, product marketing manager, Synopsys
|Samsung and Synopsys Discuss 20nm readiness|
Challenges brought on by the 20nm process node are many. Synopsys’ Andy Biddle asks Samsung’s KK Lin for his insights from the foundry perspective.
Kuang-Kuo (KK) Lin, director Foundry Design Enablement, Samsung Electronics
Andy Biddle, product marketing manager, Synopsys
|Antun Domic on 20nm challenges and Synopsys solution|
The semiconductor industry continues its relentless march towards smaller geometries. Currently, there's a big buzz around 20nm and even smaller process nodes. Watch this video to hear Antun Domic's perspective on the industry's move to advanced nodes and what it means for Synopsys. Hint: Having an industry-leading in-design solution to tackle the needs of 20nm is one way to help alleviate the challenges.
Antun Domic, senior vice president and general manager, Implementation Group, Synopsys
Swami Venkat, senior director of marketing, Galaxy Implementation Platform, Synopsys
|3D FinFET - New Structure Extends the Life of the Transistor|
MOSFETs are undergoing the most drastic transformation in nearly 50 years. What's driving this change and how will the move to 3D FinFET impact IC technology? What are these new transistors? What demands will they place on EDA tools and the design community? Professor Hu will provide insight into the driving factors behind these new transistors and how these transistors will enable the continued use of existing infrastructures of circuit and system designs, as well as device fabrication, for decades to come.
Dr. Chenming Hu, Professor Emeritus & Former CTO TSMC, UC Berkeley